Skip to main content

Full text of "westernDigital :: WD100x :: 61-031050-0030 WD1002-05 HDO OEM Manual Jul83"

See other formats


PRELIMINARY 



WD1002-05/HDO 

Winchester /Floppy Disk 

Controller 

OEM Manual 



Document No.: 61-031050-0030 



WESTERN DIGITAL 

CORPORATION 

2445 McCabe Way 

Irvine, California 92714 

(714) 863-0102 

TWX 910-595-1139 

July 1983 



TABLE OF CONTENTS 



SECTION 1 INTRODUCTION 



1 1 n^or^rirkfirkn 1-1 

I ■ I b*WWWI l|^LI^SI 1 .........................,.■■■■■■■■■■■■■■ 

1.1.1 On-Board Processing and Control Devices 1-1 

1.1.2 Communications Between Host and WD1 002-05 1-2 

12 Specifications 1-3 

1.2.1 Performance 1-3 

1.2.2 Physical 1-3 

1.2.3 Environmental 1-3 



y£y I I^^I^S jfc IBM 1 CniAvC ^^^^|^|^jt^^ I Unw 



SECTION 4 



2.1 Organization 2-1 

2.2 Host Interface Connector Signals 2-1 

2.3 40-Pin Host Interface Connector 2-1 

2.4 Winchester Drive Control Signals 2-1 

2.5 5.25" Winchester 34-Pin Drive Control Connector 2-2 

2.6 Winchester Drive Data Connector 2-2 

2.7 Power Connector 2-3 

2.8 Floppy Drive Signals 2-3 

2.9 5.25" Floppy 34-Pin Drive Control Connector 2-4 



SECTION 3 INTERFACE TIMING 



3.1 Host Interface Timing 3-1 

3.1.1 Host Task File Read Timing 3-1 

3.1.2 Host Task File Write Timing 3-1 

3.1.3 Host Sector Buffer Read Timing 3-2 

3.1.4 Host Sector Buffer Read Timing (Long Mode) 3-3 

3.1.5 Host Sector Buffer Write Timing 34 

3.1.6 Host Sector Buffer Write Timing (Long Mode) 3-4 

3.2 Miscellaneous Timing 3-5 

HOST INTERFACING 

4.1 General 4-1 

4.2 Host Interface Example 4-1 



SECTION 5 TASK FILE 



5.1 Task File Basics 5-1 

5.2 Data Register 5-1 

5.3 WD1002-05 Error Register 5-1 

5.4 Diagnostic Errors 5-2 

5.5 Write Precomp 5-2 

5.6 SectorCount 5-2 

5.7 Sector Number 5-2 

5.8 Cylinder Number 5-2 

5.9 SDH Register 5-2 

5.10 Status Register 5-3 

5.1 1 Command Register 5-4 



in 



SECTION 6 COMMANDS 

6.1 General 6-1 

6.2 WD1002-05 Command Summary 6-1 

6.2.1 Stepping Rates 6-1 

6.3 Type I Commands 6-2 

6.3.1 Test Command 6-2 

6.3.2 Restore 6-2 

6.3.3 Seek 6-2 

6.4 Type II Commands 6-2 

6.4.1 Read Sector 6-2 

6.4.1.1 Readlong Command 6-2 

6.4.1.2 DMA Read 6-3 

6.4.1.3 Normal Completion 6-3 

6.5 Type III Commands 6-3 

6.5.1 Write Sector 6-3 

6.5.1.1 Writelong Command 6-3 

6.5.2 Format Track 6-3 

SECTION 7 PROGRAMMING 

7.1 General 7-1 

7.2 Setting Up Task Files 7-1 

7.2.1 Cylinders and Tracks 7-1 

7.3 Type I Command Programming 7-1 

7.3.1 Use of Busy Bit 7-1 

7.3.2 Use of Interrupts 7-2 

7.3.3 Use of Error Bit 7-2 

7.3.4 Use of Corrected Bit 7-2 

7.4 Type II Command Programming 7-2 

7.4.1 DMA Mode 7-2 

7.4.2 Block Moves 7-2 

7.4.3 Using DMA 7-3 

7.4.4 Multiple Sector Transfers 7-3 

7.4.4.1 Partial Sector Transfers 7-3 

7.4.4.2 Interrupt Source Selection 7-3 

7.4.4.3 Clearing Hardware DRQ 7-3 

7.4.4.4 Interrupt Selection Circuit 7-3 

7.4.5 Simulated Completions 7-4 

7.5 Type III Command Programming 7-4 

7.5.1 Formatting 7-4 

7.5.2 Interleaving 7-5 

7.6 Bad Block Mapping 7-5 

7.6.1 Sector Pre-AI location 7-5 

7.6.2 Alternate Tracks 7-6 

7.6.3 Spare Sectors 7-6 

7.6.4 Bad Block Bit 7-6 



IV 



SECTION 8 THEORY OF OPERATION 

8.1 Generai 8-1 

8.2 WD1002-05 Architecture and Functional Description 8-1 

u.c\ nuoi unci iaoc i_uyiC \nii_; o- i 

8.2.2 Control Processor(CP) 8-3 

8.2.2.1 Clock Generator 8-3 

8.2.2.2 Task/Syndrome File (TSF) 8-3 

8.2.3 Error Detection and Support Logic (EDS) 8-3 

8.2.3.1 Error Detection 8-3 

8.2.3.2 Support Logic 8-4 

8.2.4 Sector Buffer (SB) 84 

8.2.5 Winchester Drive and Buffer Interface (WDBI) 84 

8.2.5.1 Write Precompensation (WPC) 8-4 

8.2.5.2 Data Separator 8-5 

8.2.6 Floppy Drive and Buffer Interface (FDBI) 8-5 

SECTION 9 MAINTENANCE 

9.1 General 9-1 

9.2 Oscillator Frequency 9-1 

9.3 WD2797 Adjustment Procedure 9-1 

9.4 Test/Operation Jumper Variations 9-1 

APPENDIX A DISK DRIVE EXAMPLES 

A.1 Introduction A-1 

A.2 Polled Status Driver A-1 

A.2.1 Initialization A-2 

A.2.2 Read Sector A-2 

A.2.3 WriteSector A-3 

A.2.4 Task File Updating A-4 

A.3 Interrupt Driven Driver A-4 

A.3.1 Initialization A-5 

A.3.2 Read Sector A-6 

A.3.3 Write Sector A-6 

A.3.4 Task File Updating A-7 

A.3.5 Interrupt Service Routine A-8 

APPENDIX B INTERLEAVE CALCULATING 

APPENDIX C CALCULATING SECTORS PER TRACK 

APPENDIX D PROGRAMMERS QUICK REFERENCE 

D.1 Task File D-1 

D.2 Valid Commands D-1 

D.3 SDH Register Format D-1 

D.4 Status and Error Register Bits D-2 



APPENDIX E LSI DATA SHEETS (to be supplied) 



APPENDIX F SCHEMATICS AND ASSEMBLY DIAGRAMS 
APPENDIX G BILL OF MATERIALS (to be supplied) 



VI 



LIST OF TABLES 

TABLE TITLE PAGE 

2-1 Host Interface Connector Pin Description 2-1 

2-2 Winchester Drive Control Connector Pin Description 2-2 

2-3 Winchester Drive Data Connector Pin Description 2-3 

2-4 Power Connector Pin Description 2-3 

2-5 Floppy Drive Control Connector Pin Description 2-4 

3-1 Host Task File Read Timing 3-1 

3-2 Host Task File Write Timing 3-1 

3-3 Host Sector Buffer Read Timing (Normal Mode) 3-2 

3-4 Host Sector Buffer Read Timing (Long Mode) 3-3 

3-5 Host Sector Buffer Write Timing (Normal Mode) 3-4 

3-6 Host Sector Buffer Write Timing (Long Mode) 3-5 

3-7 Miscellaneous Timing 3-5 

5-1 Task File Register Array 5-1 

5-2 Error Register Bits 5-1 

5-3 SDH Register 5-3 

5-4 SDH Bits6&5 5-3 

5-5 SDH Bits 4 & 3 5-3 

5-6 SDH Bits2, 1 &0 Hard Disk 5-3 

5-7 SDH Bits 2, 1 &0 Floppy Disk 5-3 

5-8 Status Register Bits 5-3 

6-1 Command Types 6-1 

6-2 r3-r0 — Stepping Rates 6-1 

7-1 File Read On 4-Head, 2-Platter Disk Drive 7-1 

7-2 Interleave Table with 32 Sectors and 4:1 Interleave 7-5 

7-3 Interleave Table with 32 Sectors and 4:1 Interleave-Physical Sector Five Mapped Out 7-6 

7-4 Interleave Table with Redundant Sectors, No Interleave, and 

All Sectors Marked as Bad Blocks 7-6 



VII 



LIST OF ILLUSTRATIONS 

TABLE TITLE PAGE 

1-1 WD1002-05 Simplified Data/Command Flow Block Diagram 1-2 

3-1 Host Task File Read Timing 3-1 

3-2 Host Task File Write Timing 3-2 

3-3 Host Sector Buffer Read Timing: Prog I/O 3-2 

3-4 Host Sector Buffer Read Timing: DMA Mode 3-3 

3-5 Host Sector Buffer Read Timing (Long Mode) 3-3 

3-6 Host Sector Buffer Write Timing (Normal Mode) 3-4 

3-7 Host Sector Buffer Write Timing (Long Mode) 3-5 

3-8 Miscellaneous Timing 3-6 

4-1 Host Interfacing Example 4-1 

7-1 Interrupt Selection Circuit 7-4 

8-1 WD1002-05/WD1002-HDO Functional Block Diagram 8-2 



IX 



SECTION 1 
INTRODUCTION 



1.1 DESCRIPTION 

The WD1002-05 Winchester/Floppy Disk Controller 
(WFC) is a stand-alone, general purpose board that 
allows a host processor to control up to three Win- 
chester 5.25-in. disk drives and four floppy 5.25-in. 
disk drives. The following is a synopsys of the 
WD1 002-05 features: 

User-selectable 5.25" Winchester or Floppy 
operation 

controls up to 3 Winchester and up to 4 Floppy 
drives 

Single + 5V Power Supply 

8-bit universal host interface 

On-Board data separation circuitry 

On-Board write precompensation for floppy and 
hard disks 

On-Board sector buffer supports up to 1K-byte 
sectors 

Programmable sector sizes — 128, 256, 512, or 
1024 bytes 

Automatic track formatting on hard and floppy 
disks 

Multiple sector operations on all disks 

Data rates up to 5 Mbits/sec on hard disk 

Single burst error correction up to 5 bits on hard 
disk data 

CRC generation/verification for data and all I.D. 
fields 

Automatic retries on all errors with simulated 
completion 

ECC diagnostic commands included (READLONG 
&WRITELONG) 

WD1 002-05 internal diagnostics 

16 different stepping rates for both hard and floppy 
drives 

The WD1002-HDO is a depopulated version of the 
WD1002-05. All Floppy drive control and associated 
circuitry has been deleted from the board, providing a 
Winchester Drive Controller board that will drive up 
to three 5 1 /4 " Winchester disk drives. All parameters, 
programming, and timing in this document that 
applied to Winchester Drive Control pertain to the 
WD1 002-05 and the WD1 002-H DO. 

All buffers and driver/receivers needed for direct con- 
nection to the disk drives are furnished as part of the 
WD1002-05 circuitry. The logic for the WD1002-05's 
variable-length sector buffer, as well as logic neces- 
sary for error correction, data separation, and host 



interface circuitry is also included. Winchester disk 
drive signals are based on the floppy disk, look-alike 
interface available with the Seagate Technology 
ST506 and other compatible drives. 

I/O connections are made with standard ribbon cable 
connectors. The disk interface connectors have 
standard pinout configurations to allow direct pin-for- 
pin connection to the Winchester and Floppy disk 
drives. Power ( + 5 VDC) and ground for the 
WD1 002-05 are furnished on a separate connector. 

1.1.1 ONBOARD PROCESSING AND 
CONTROL DEVICES 

The WD1 002-05 consists of a set of devices spec- 
ifically designed for host dual control of Winchester 
and Floppy disk drives. The heart of the control logic 
is the Control Processor Buffer Manager (WD1015) 
that manages the on-board static RAM sector buffer 
(2048-word-by-8-bit). All bytes of data written to, and 
read from disk is first stored in this sector buffer. 
When the buffer is full, the data is transferred, on 
command, to its intended destination. 

The WD1015, besides controlling data flow between 
host, sector buffer, and disk controllers, ajso trans- 
lates the host Winchester command format to Flop- 
py disk format When addressing the Floppy Disk 
Controller (WD2797). This permits the host to main- 
tain a single command format (Winchester) while in 
effect controlling two different disk command for- 
mats (Winchester vs. Floppy). This is possible since 
the SDH register is used to select either type of drive. 

The WD1015 maintains the current copies of neces- 
sary host command data in the task files; a set of 
registers physically located in the Winchester Disk 
Control device (WD1010) and the Error Detection and 
Support logic device (WD1014). 

The WD1010 is the link between the host processor 
(via sector buffer) and the Winchester disk drives. 
During transfer of data from the host to the WD1010 
the WD1014 computes a 4-byte ECC which is ap- 
pended to the end of the data being transferred to the 
WD1010 and recorded on disk. During data transfers 
from the WD1010 to the host (via the sector buffer), 
the WD1015 uses the ECC syndrome to validate the 
data. Retries and corrections are attempted auto- 
matically in case of corrupted data. 

The WD1015 performs error correction in conjunction 
with the WD1014 on data transferred to the disk. 
While the WD1015 controls the operation of the on- 
board error-correction logic, the WD1014 generates 
and checks the Error Correction Code (ECC) if SDH 
bit 7 = 0. Thus the WD1014 also provides the 
WD1015 its reai-time control capability. Specifically, 



1-1 



the real-time function is provided for Winchester disk 
operation only {real-time function is not available for 
Floppy disk operation). 

If CRC format Winchester disks are used, CRC is se- 
lected by the WD1010 by setting SDH7 = 0. CRC for 
the floppy disks is performed by the WD2797, a de- 
vice that furnishes all control functions for floppy 
disk drives, including necessary data separation and 
write precompensation. SDH7 must be set to zero for 
floppy disk operation. 

A simplified data flow and command flow block dia- 
gram is illustrated in Figure 1-1. 

1.1.2 COMMUNICATIONS BETWEEN HOST 
AND WD1002-05 

Two-way communications between the host pro- 
cessor and the WD1 002-05 is via a parallel access 
port and an 8-bit, bi-directional bus. Appropriate con- 
trol signals are used to transmit disk READ/WRITE 
data, status information, and macro commands over 
the data bus. 

Communications between the host processor and 
the WD1002-05 uses_eight data bus lines (DAL7- 
DALO), a Card Select (CS), a Read Enable (RE), a Write 
Enable JWE), three address lines (A2-A0), a Master 
Reset (MR), a Data ReQuest (DRQ), and an INTerrupt 
ReQuest (INTRQ). (See SECTION 2 for a complete 
description of control signals.) 



The Master Reset strobe (MR) must be used to 
initialize the WD1 002-05 on power-up. This always 
initiates the internal diagnostics of the WD1002-05 
and no command may be processed until the BUSY 
bit is cleared (approx. 1-2 seconds). 

To communicate with the WD1 002-05, the host pro- 
cessor must first access a set of registers called the 
task files (see SECTION 5 for a description of the task 
file registers and SECTION 7 for programming in- 
formation). All parameters necessary for a command 
to be executed are set into the task files. The task 
files tell the WD1 002-05 what is to be done, i.e. sector 
size to be selected, disk drive selected and head or 
side desired, sector number, and any other 
information needed to execute the command. 

After a command has been issued, the host can 
verify that the command has been executed either by 
polling the BUSY bit in the task file or by waiting for 
an interrupt request (See SECTION 6 for description 
of commands). 

For all write operation commands, including format, 
the host must fill up the sector buffer no less than 
the sector size chosen, otherwise the WD1002-05 will 
not execute the command. The sector buffer need 
only contain the required valid data to execute the 
command while the rest of the bytes serve as fillers 
(especially for a format operation). Once the sector 
buffer is filled all communications with the host are 



O 



HOST 

INTERFACE 

LOGIC 




DATA BUS 



WD1015 

CONTROL 

PROCESSOR 



ADDR 
LOGIC 



} 



sz 



SECTOR 
BUFFER 



5Z 



7\ 



WD1014 
EDS 



ZY 



CONTROL BUS 



N. WD2797 y/1 N. 

I ) FLOPPY C y 

] 1/^ CONTROLLER ^ y 



u 



FLOPPY 
IFC 



"NOTONWD1002-HDO 






J> 



L .K wdioio yu\ data y^\ OT > 

} WINCHESTER f ) SEP ( J i ll 

1 ~y CONTROLLER \fy LOGIC \j"y % ~ 



Figure 1 -1 . WD1 002-05 Simplified Data/Command Flow Block Diagram 



1-2 



terminated. 

Multiple transfer commands are handled one sector 
at a time. If the host wants to transfer ten sectors, the 
WD1002-05 sequentially accepts one sector of data at 
a time and processes it until all sectors have been 
transferred. .At the com n !etion of the multinie 
transfer, the interrupt request is set, and the BUSY bit 
is cleared. 

1.2 SPECIFICATIONS 



The data request (DRQ) will always be set at the start 
of a write command, indicating that the sector buffer 
is available for sequentially inputting data. If the data 
request is set on a read command, it indicates that 
data requested by the host is in the sector buffer. 

The interrupt request (INTRQ) is set after completion 
of a command. Status and error information may now 
be read by the host. 



1.2.1 PERFORMANCE 






DRIVE PARAMETERS 


WINCHESTER DISKS 


FLOPPY DISKS 


Encoding method: 


MFM 


MFM 


Cylinders: 
Sectors per track: 
Heads: 


Up to 1024 
Up to 64 
8 


Up to 256 
Up to 64 
2 


Drive selects: 


3(ST506) 


4(SA450) 


Step rate: 


35 pts to 7.5 ms (500 ^sec 
increments) 


~15ns, 1ms, 2ms, 3ms, 4ms, 5ms, 
6ms, 8ms, 10ms, 12ms, 14ms, 16ms, 
18ms, 20ms, 25ms, 40ms. 


Data transfer rate: 


5.0 Mbits/s 


250 Kbits/s 


Write Precomp time: 
Sectoring: 


12 ns 
Soft 


100 to 300 ns adj. 
Soft 



CRC polynomial: 
ECC polynomial: 
ECC polynomial reciprocal: 



General 

X16 + x12 + X5 + 1 

X 32 + x28 + x26 + x19 + X17 + X™ + X6 + X2 + 1 

X 32 + x30 + x26 + x22 + x15 + X"I3 + X6 + X4 + 1 





256 byte sector 


512 byte sector 


Non-detection probability: 
Miscorrection probability: 
Correction span: 
Single burst detection span: 
Double burst detection span: 


~2.30E-10 
8.00 E-6 
5 bits 
20 bits 
4 bits 


~2.30E-10 
1.57 E-5 
5 bits 
19 bits 
3 bits 


Host interface: 
Drive capability: 
Drive cable length: 
Host cable length: 
Power requirements: 


8-bit bi-directional bus 

10 LS loads 

10 ft max 

3 ft max 

+ 5V ± 5%, 3.0 A max 




MTBF: 
MTTR: 


10,000 POH 
30 min. 




1.2.2 PHYSICAL 






Length: 

Width: 

Height: 


8.00 in. 
5.75 in. 
0.75 in. 




1.2.3 ENVIRONMENTAL 






Ambient temperature 


0-50°C 





Relative Humidity (non-condensing) .... 20% -80% 

Air flow at 1/4" from component surfaces . . 150 cubic ft/min 



1-3 



SECTION 2 
INTERFACE CONNECTORS 



2.1 ORGANIZATION 

The WD1 002-05 board has seven connectors for user 
application: 

(J6) Power connector 

/ IR\ l_l/~io+ In+orfooo r*mnnas\i-r\r 
yj^J/ i iuoi ii nui iuuo v/v/i n icv/iui 

(J7, J8) Drive control connectors 

(J1, J2, J3) Winchester high speed data connectors 

The drive control cables are daisy-chained to each of 
the three Winchester drives. The three drive data con- 
nectors carry differential signals and are radially 
connected. 

2.2 HOST INTERFACE CONNECTOR SIGNALS 

The signals of the host interface connector (J5) are 
compatible with most microprocessors and many 
minicomputers. The connector consists of an 8-bit bi- 
directional bus, a 3-bit address bus, and seven 
control lines. All commands, status, and data are 
transferred over this bus. The control signals are as 
follows: 



DAL0-DAL7 



CS 



WE 



RE 



A2-A0 



INTRQ 



DRQ 



8-bit bi-directional Data Access 
Lines. These lines are in a high-im- 
pedance state whenever the CS line 
is inactive. 

When Card Select (CS) is active 
aiong with RE or WE, data is read or 
written via the DAL bus. 

When Write_Enable (WE) is active 
along with CS, the host may write 
data to a selected register of the 
WD1002-05. 

When Read_Enable (RE) is active 
along with CS, the host may read 
data from a selected register of the 
WD1 002-05. 

Three Address lines are used to 
select one of eight registers of the 
WD1002-05. They must remain stable 
during all read and write operations. 

The INTerrupt ReQuest line is acti- 
vated whenever a command has 
been completed. It is reset to the in- 
active state when the status register 
is read, or a new command is issued 
to the WD1002-05, or when MR is 
asserted. 

The Data ReQuest line is activated 
whenever the sector buffer contains 
data to be read by the host, or is 
awaiting data to be loaded by the 



host. This line is reset whenever the 
sector buffer is exhausted, or when 
MR is asserted. 

MR The Master Reset (MR) line initializes 

all internal jogic on the WD1 002-05. 
Whenever MR is received by the 
WD1002-05, the internal diagnostics 
are automatically initiated. 

GND All even numbered pins on this 

connector are to be used as signal 
grounds. Power grounds are avail- 
able on the power connector. 

2.3 40-PIN HOST INTERFACE CONNECTOR 

The host interface connector (J5) is a 40-pin vertical 
header. Cabling should be less than three feet long. 
Either flat ribbon or twisted pair cable can be used. 
The connector pinouts are given in Table 2-1. 

Table 2-1 . Host Interface Connector Pin Description 



Signal 


Signal 




Ground 


Pin 


Signal Name 


2 


1 


DAL0 


4 


3 


DAL1 


6 


5 


DAL2 


8 


7 


DAL3 


10 


9 


DAL4 


12 


11 


DAL5 


14 


13 


DAL6 


16 


15 


DAL7 


18 


17 


A0 


20 


19 


A1 


22 


21 


A2 


24 


23 


CS 


26 


25 


WE 


28 


27 


RE 


30 


29 


Pull-up (PUP) 


32 


31 


Not Connected 


34 


33 


Not Connected 


36 


35 


INTRQ 


38 


37 


DRQ 


40 


39 


MR 



2.4 WINCHESTER DRIVE CONTROL SIGNALS 

The Winchester Drive Control connector (J7) is a 
relatively low-speed bus, daisy-chained to each of the 
Winchester drives in the system. To properly term- 
inate the open collector outputs from the WD1002-05, 
the last drive in the daisy chain should have a 220/ 
330-ohm line termination resistor pack installed. All 
other drives should have no termination. Drive con- 



2-1 



trol signals are as follows: 



RWC 



WG 
SC 



TR000 



WF 



HS2-HS0 



IND 



RDY 



STEP 



When the Reduce Write Current 
(RWC) line is activated with write 
gate, a lower write current is used to 
compensate for greater bit-packing 
dens ity on the inner cylinders. The 
RWC line is activated when the cyl- 
inder number is greater than or equal 
to four times the contents of the 
write precomp register. This output is 
valid only during write and format 
commands. 



The Write Gate signal enables the 
disk write data circuitry. 

Seek Complete line informs the 
WD1 002-05 that the head of the se- 
lected drive has reached the desired 
cylinder and h as stabilized. Since 
Seek Complete is not checked after a 
seek command, overlapped seeks 
are allowed. 

TRack 000 indicates that the R/W 
heads are positioned on the outer- 
most cylinder. This line is sampled 
before each step pulse is issued. 

Write Fault informs the WD1 002-05 
that some fault has occurred on the 
selected drive. The WD1002-05 will 
not execute commands when this 
signal is true. 

Head Select lines (HS2-HS0) are used 
by the WD1 002-05 to select a specific 
R/W head on the selected Winches- 
ter drive. 



Index is used to indicate the index 
point for synchronization during for- 
matting and as a timeout mechanism 
for retries. This signal should pulse 
once every rotation of the disc. 

Ready informs the WD1 002-05 that 
the desired drive is selected and that 
its motor is up to speed. The 
WD1002-05 will not execute com- 
mands unless this line is true. 



Step is pulsed once for every cylinder 
to be stepped. The direction of the 
step will be determined by the direc- 
tion tine. The Step pulse period is 
determined by the internal Win- 
chester stepping rate register during 
implied seek operations, or explicitly 
during seek commands. During auto 



restore, the step pulse period is de- 
termined by the seek complete time 
from the drive. 

DS1-DS3 These th ree Drive Select lines 

(DS1-DS3) are used to select one of 
three possible drives. 

DIRIN Direction In determines the direction 

of motion of the R/W head when the 
step line is pulsed. A high on this line 
defines the direction as out, and a 
low defines direction as in. 

2.5 5.25" WINCHESTER 34-PIN DRIVE 
CONTROL CONNECTOR 

This drive control connector (J7) is a 34-pin vertical 
header on 0.10-inch centers. Cabling should be flat 
ribbon or twisted-pair cable less than 10 feet long. 
The cable pinouts are given in Table 2.2. 

Table 2-2. Winchester Drive Control Connector 
Pin Description 



Signal 


Signal 






Ground 


Pin 


I/O 


Signal Name 


1 


2 





RWC 


3 


4 





Head Select 2 


5 


6 





Write Gate 


7 


8 


I 


Seek Complete 


9 


10 


I 


TR000 


11 


12 


I 


Write Fault 


13 


14 





Head Select 


15 


16 




NC 


17 


18 





Head Select 1 


19 


20 


I 


Index 


21 


22 


I 


Ready 


23 


24 





Step 


25 


26 





Drive Select 1 


27 


28 





Drive Select 2 


29 


30 





Drive Select 3 


31 


32 




NC 


33 


34 





Direction In 



2.6 WINCHESTER DRIVE DATA CONNECTOR 

Three data connectors (J1-J3) allow data to pass 
between the WD1 002-05 and each Winchester disk 
drive. All lines associated with the transfer of data 
between a drive and the WD1 002-05 system are differ- 
ential in nature and may not be multiplexed. The 
three Winchester drive data connectors are 20-pin 
vertical headers on 0.10-inch centers. Cabling should 
be either fiat ribbon or twisted-pair cable, less than 10 
feet long. Cable pinouts are given in Table 2-3. 



2-2 



Table 2-3. Winchester Drive Data Connector 
Pin Description 



DS3-DS0 



Sianal 


Sianal 






Ground 


Pin 


I/O 


Signal Name 


2 


1 




NC 


4 


3 




NC 


6 


5 




NC 


8 


7 




NC 




9 




NC 




, 10 




NC 


11 






GND 


12 






GND 




13 





MFM Write Data 




14 





MFM Write Data 


15 






GND 


16 






GND 




17 


I 


MFM READ Data 




18 


I 


MFM READ Data 


19 






GND 


20 






GND 



2.7 POWER CONNECTOR 

A 4-pin amp connector (J6) is provided for power and 
ground inputs to the board. The pinouts are given in 
Table 2-4. 

Table 2-4. Power Connector Pin Description 



Pin 


Signal Name 


1 
2 
3 
4 


NC 

GROUND 

GROUND 

+ 5V regulated @ 3 amps (max) 



2.8 FLOPPY DRIVE SIGNALS 

The Floppy Drive Control connector (J8) is a relatively 
low-speed bus, daisy-chained to each of the floppy 
drives in the system. To properly terminate each TTL- 
level output signal from the WD1 002-05, the last drive 
in the daisy chain should have line terminations as 
specified by the drive manufacturer. The other drives 
should not have any terminations. Drive control sig- 
nals for the floppy discs are functionally similar to 
those for the hard discs, except that all data is 
transferred via one connector instead of the separate 
connectors used for the Winchester drives. Floppy 
drive signals are as follows: 



IND 



The Index line contains a reference 
index pulse once every disk rotation 
to indicate the beginning of a track. 



IVIU 



DIRIN 



STEP 



WD 



WG 



TR000 



WP 



These f our Drive Select lines 
(DS3-DS0) are used to select one of 
four possible drives. 

1 1 It? IVIUIUI KJl\ line id uocu iu uiicouy 

control the dc spindle motor of the 
floppy drive, if Motor On Mode 
(MOM) = (user selectable jumper 
option) then a 40 nsec delay occurs, 
otherwise a one-second delay occurs 
after Motor On and before any read- 
ing or writing is attempted. If the flop- 
py drive is not accessed for ~3 
seconds, the motor is turned off by 
the WD1015. Also the drives sup- 
ported must be configured so that 
the R/W heads are loaded when the 
motor is turned on. This is usually 
available as an option on most drives. 

The Direction In line determines the 
direction of motion of the R/W head 
when the step line is pulsed. A high 
on this line defines the direction as 
out, and a low defines the direction 
as in. 



The Step line is pulsed once for each 
cylinder to be stepped. The direction 
of the step will be determined by the 
direction line. The step pulse period 
is determined by the internal floppy 
stepping rate register during implied 
seek operations, auto restore, or ex- 
plicitly during seek and restore com- 
mands. During any restore operation, 
the stepping-rate period is limited to 
8 ms minimum. 



The Write Data interface line pro- 
vides data to be written on the disk. 
This line is enabled by write gate 
being active. 

The Write Gate output signal enables 
disk write data circuitry. 



TR000 indicates that the R/W heads 
are positioned on the outermost cyl- 
inder. This line is sampled before 
each step is issued. 

The Write Protect interface signal 
provided by the drive indicates to the 
WD1 002-05 that a write-protected 
disk is installed. When write protect 
is active, no data can be written to 
the disk by the WD1 002-05. 



2-3 



RD 



SS 



The Read Data line provides the "raw 
data" (clock and data together) as de- 
tected by the drive logic. 

Selects side of floppy disk to be 
written or read. 



Table 2-5. 



2.9 5.25" FLOPPY 34-PIN DRIVE CONTROL 
CONNECTOR 

This floppy drive control connector (J8) is a 34-pin ver- 
tical header on 0.10-inch centers. Cabling should be 
flat ribbon or twisted-pair cable, less than 10 feet 
long. The cable pinouts are given in Table 2-5. 



Floppy Drive Control Connector 
Pin Description 



Signal 


Signal 






Ground 


Pin 


I/O 


Signal Name 


1 


2 





NC 


3 


4 


— 


NC 


5 


6 





Drive Select 


7 


8 


I 


Index 


9 


10 





Drive Select 1 


11 


12 





Drive Select 2 


13 


14 





Drive Select 3 


15 


16 





Motor On 


17 


18 





Direction In 


19 


20 





Step 


21 


22 





Write Data 


23 


24 





Write Gate 


25 


26 


I 


Track 000 


27 


28 


I 


Write Protect 


29 


30 


I 


Read Data 


31 


32 





Side Select 


33 


34 


— 


NC 



2-4 



SECTION 3 
INTERFACE TIMING 



3.1 HOST INTERFACE TIMING 



3.1.1 HOST TASK FILE READ TIMING 

The task files read by the host are physicaiiy iocated 
in the WD1010 Winchester Disk Controller. The error 

reyisiei is iuucu6u in me »vu iu i*+ luo ucviuc, anu mc 

status register is implemented using TTL gates. 
Table 3-1 . Host Task File Read Timing 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


tSET 


Addr, Card select setup to RE 


200 




ns 


tHLD 


Addr, Card select hold from RE 







ns 


tRE 


Read enable pulsewidth 


0.4 


10 


MS 


tRDR 


Read Recovery time 


300 




ns 


tDA 


Data access after RE active 




400 


ns 


tDH 


Data hold after RE inactive 




25 


ns 



ADDR 



CS 



X 



A ,A-|,A 2 STABLE 



X 



l HLD 



X 



-tSET- 



I^H-tRDR-^k 



RE 



DBO-7 



N^ 



■tRE' 



jri 



■ 4 DA 



3: 



■tDH 



DATA VALID 



> 



Figure 3-1 . Host Task File Read Timing 



3.1.2 HOST TASK FILE WRITE TIMING 

The task files written to by the host are physically 
located in the WD1010 device except for the com- 
mand register, which is located in the WD1014 EDS 
device. 



Table 3-2. Host Task File Write 


Timing 








SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


tSET 


Addr, Card select setup to WE 


0.1 


10 


MS 


tHLD 


Addr, Card select hold from WE 


30 




ns 


tWE 


Write enable pulsewidth 


0.2 


10 


M s 


tWER 


Write Recovery time 


1.0 




MS 


tDS 


Data access setup to WE active 


0.2 


10 


MS 


tDH 


Data hold after WE inactive 


10 




ns 



3-1 




Figure 3-2. Host Task File Write Timing 



3.1.3 HOST SECTOR BUFFER READ TIMING 

After a read command, the host can read the sector 
buffer by accessing the data register. The DRQ line is 
set at the start of every sector transfer and is reset 
when the sector buffer has been emptied. 

Table 3-3. Host Sector Buffer Read Timing (Normal Mode) 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


tRC 


Read Cycle time 


337 




ns 


tACC 


Addr, Card select to Data Valid 




337 


ns 


tRE 


Read enable pulsewidth 


200 




ns 


tRR 


Read Recovery time 




137 


ns 


*DA 


Data access from RE active 




200 


ns 


tDH 


Data hold after RE inactive 




25 


ns 



•tRC- 



CS, ADDRESS 



RE 



* 



X 



-Ucc- 



l RR f 



^ 



-*DA- 



■tRE- 






■tDH 



D OUT 



, )X OUTPUT DATA VALID,, 



UNKNOWN 



Figure 3-3. Host Sector Buffer Read Timing : Prog I/O 



3-2 





ADDR, CS 

nc: 

DOUT — 


r* tRC 

1 ( 


i 


. , .„ .,„ ., ,// 




• 




X ! 


i 




Ws 


X 

1 
1 

• 




'r<— tACC— »1 1-^-tRR-^j 
. ' -?1 tDA K-! _ 


i 
1 

X 


/J 

17 A 


\ ' X \ 

\ , /■ \ 






<8k m-m 




MWs <v 




D® — 


_rW tf 













Figure 3-4. Host Sector Buffer Read Timing : DMA Mode 



3.1.4 HOST SECTOR BUFFER READ TIMING 
(LONG MODE) 

In the long mode of sector buffer read timing, the 
host reads four extra check bytes after the sector 
buffer has been emptied. These bytes are actually 
read from the WD1014 EDS device and not from the 



sector buffer. The host is only required to generate 
four additional read strobes subject to the timings in- 
dicated. Multiple sector transfers are also permitted. 

DMA data transfer speed should be limited in order 
to read the four check bytes in this special diagnostic 
mode. 



Table 3-4. Host Sector Buffer Read Timing (Long Mode) 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


tRP 


Read Cycle time . 


800 




ns 


tAS 


Address setup to CS 







ns 


tAH 


Address hold from CS 







ns 


tcs 


Card select setup to RE 







ns 


tCH 


Card select hold to RE inactive 







ns 


tACC 


Addr, Card select to Data Valid 




237 


ns 


tRE 


Read enable pulsewidth 


50 




ns 


tDA 


Data access from RE active 




100 


ns 


tDH 


Data hold after RE inactive 




25 


ns 



ADDR 
CS 

RE 
D OUT 
















X $ 

1 1 
1 1 

-*►! t A s U — j -»J t AH l«- 






■m 




X 


j N L4 

i i i ! 
ii, ii 

j — +A tcs r* — *RE — ► l CH h* — 

1 ' ' 




\ 


r 

1 

1 

1 




1 > — f 




- T RP- 


\ 






1 1 It 1 
— ^| *DA f*- -► j t DHJ-* 


$$/ ' Hfl& 


ZD®- 


Wk w& 















Figure 3-5. Host Sector Buffer Read Timing (Long Mode) 



3-3 



3.1.5 HOST SECTOR BUFFER WRITE TIMING 

After a write or a format command has been issued, 
the host can write to the sector buffer by accessing 
the dat a register. Both the address lines A2-A0, and 
the CS line can be held in their active states without 
being toggled while writing the sector of data. The 

Table 3-5. Host Sector Buffer Write Timing (Normal Mode) 



DRQ line is set at the start of every data transfer and 
is reset when the SB has been filled. 

The DMA write cycle timing diagram is similar to the 
DMA read cycle timing shown in Figure 3-4. 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


twc 


Write Cycle time 


257 




ns 


tAS 


Address setup time 







ns 


tew 


Addr, Card select to end of WE 


257 




ns 


tWE 


Write enable pulsewidth 


120 




ns 


tWR 


Write Recovery time 




137 


ns 


tDS 


Data access from WE active 


60 




ns 


tDH 


Data hold after WE inactive 


15 




ns 



■ twc- 



ADDRESS 



X 



X 



Se 7, 



- l CW- 



4\\\\\\\\\\\\\ 



= wwwwvKwwwv 



IM//M///////////, 



WE 



l-^tAS-^l 



■ t WE . 



wm 



►I t WR u 
-) i 



i 
i 
i 



■tDS- 



"j tDH |- 



D|N 



X 



DATA IN STABLE 



X 



Figure 3-6. Host Sector Buffer Write Timing (Normal Mode) 



3.1.6 HOST SECTOR BUFFER WRITE TIMING 
(LONG MODE) 

In the long mode of sector buffer write timing, four 
extra check bytes are written by the host after the 
sector buffer has been filled. The bytes are actually 
written to the WD1014 EDS device and not to the sec- 
tor buffer The host is required to generate four addi- 
tional write strobes subject to the timings indicated. 
Muttipfe sector transfers are permitted. 

DMA data transfer speed should be limited in order 
to write the four check bytes in this special diagnos- 
tic mode. 



3-4 



BUSY 



INTRQ 



DRQ 



MR 



"V 



U-*iv 



> 



|^-tDV-^-| 



■tBS — ►! 

1 X 

-i A 



t|R 



U-< 



x 



•to a- 



X 



I 

-tMR- 



X 



^j t|RW 

WE (CMD. WRITE) N ^ | / 

—►I t|RR f* — 

RE (STATUS) K ' / 

I 1 

I 



INTRQ 



X 



WE 



RE 



DRQ 



CMD. 



X~frX ^TE '/ 



1 it LAST ' , 



*DSW — *\ \*- tDRW-^l |«<- 



X. 



Figure 3-8. Miscellaneous Timing 



3-6 



3ECTI0N ^ 

HOST INTERFACING 



4.1 GENERAL 

The WD1 002-05 easily interfaces with most micro- 
computers and many minicomputers. Interfacing is 
accomplished with the host interface connector (J5). 

The interface is very similar to that used for other 
Western Digital LS! peripheral devices, and the signal 
pinouts are compatible with the Western Digital 
WD1000 and WD1001 series of Winchester Disk Con- 
troller boards. 



The W AIT line is not used in the WD1002-05. The 
WAIT signal, however, is still provided for com- 
patibility with WD1000 and WD1001 controllers. 



4.2 HOST INTERFACING EXAMPLE 

Figure 4-1 shows the absolute minimum hardware re- 
quired to interface the WD1002-05 board to a small 
8085 microcomputer system. In the illustration, buf- 
fers are not used, nor is the I/O completely decoded. 
The user will most likely want to completely decode 
the I/O to minimize the amount of I/O or memory 
space required in the host for WD1002-05 interfacing. 
If the interface cable length is kept to a few inches, it 
is often possible to directly interface the WD1002-05 
to the buffered bus of a host microcomputer. 











^ 


■s 


V- 


"1 






RESOUT 

READ 

WR 

RD 

A15 

8085 

ALE 
AD7 
AD6 
AD5 
AD4 
AD3 
AD2 
AD1 
ADO 




\^ 


1 


MR 
WAIT 

We 

RE 

CS 

DAL7 

DAL6 

DAL5 

DAL4 

DAL3 

DAL2 WD1002 

DAL1 

DALO 

INTRQ 
DRQ 

A2 
A1 
A0 
+ 5GND -V 




















r^ 








^O^ 




( 




/°^ 


r 


74LS373 


<" 


r 


f 


r 








r 




G 

8D 8Q 
7D 7Q 
6D 6Q 
5D 5Q 
4D 4Q 
3D 3Q 
2D 2Q 
1D 1Q 
QC 




<■ 


> 








^ 




> 




v 




> 


"> 




> 


> 




> 


^ 




^ 


> 




"S 






^ 




> 






> 




^ 


J 












^ 

^ 


u 




AC 


-7 









Figure 4-1 . Host Interfacing Example 



Table 3-6. Host Sector Buffer Write Timing (Long Mode) 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


twp 


Write Cycle time 


800 




ns 


tAS 


Address setup to CS 







ns 


tAH 


Address hold from CS 







ns 


tcs 


Card select setup to WE 







ns 


tCH 


Card select hold to WE inactive 







ns 


tWE 


Write enable pulsewidth 


50 




ns 


tDS 


Data setup to WE inactive 


60 




ns 


tDH 


Data hold after WE inactive 


15 




ns 



ADDR 



CS 



WE 



X 



X 



X 



*AS 



l AH 



1 



f 



\ 



/ 



1 . i ' 

<CS \*— 'WE *• <CH 



\ 



X 



-t W p. 



\ f 

. I 



U-tDS-^jtDH} 



°.n mwwwmw 



mwwwwwww 



m\\\\\\\\\w 



Figure 3-7. Host Sector Buffer Write Timing (Long Mode) 



3.2 MISCELLANEOUS TIMING 



Table 3-7. Miscellaneous Timing 



SYMBOL 


CHARACTERISTIC 


MIN. 


MAX. 


UNITS 


tiv 


INTRQ valid from BUSY inactive 




60 


ns 


tDV 


DRQ valid from BUSY inactive 




60 


ns 


tMR 


Master Reset pulsewidth 


50 




ms 


tBS 


MR to BUSY set 




200 


ns 


t|R 


MR to Interrupt reset 




200 


ns 


tDR 


MR to Data request reset 




200 


ns 


t|RW 


WR (cmd.) to Interrupt reset 




200 


ns 


t|RR 


RE (status) to Interrupt reset 




200 


ns 


tDSW 


Write command to DRQ set 




200 


ns 


tDRW 


WE/RE to DRQ reset 




300 


ns 



3-5 



SECTION 5 
TASK FILE 



5.1 TASK FILE BASICS 

The WD1002-05 performs all disk functions through a 
set of registers called the task files. The task files are 
loaded with parameters such as sector number, 
cylinder number, etc., prior to issuing a command. 



Individual registers are selected via A0-A2 for both 
types of drives. The registers shown in Table 5-1 are 



Table 5-1 . Task File Register Array 



CS 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


Deselected 


Deselected 















1 




1 




Data Register 
Error Register 
Sector Count 


Data Register 
Write Precomp* 
Sector Count 








1 


1 


Sector Number 


Sector Number 







1 
1 
1 





1 




1 




Cylinder Low 
Cylinder High** 
Size/Drive/Head 


Cylinder Low 
Cylinder High** 
Size/Drive/Head 





1 


1 


1 


Status Register 


Command Register 



*Not used on floppies 
* * LSB of cylinder high, if set to 1 , permits a 48 t.p.i. floppy disk to be read on a 96 t.p.i. floppy disk system. 



5.2 DATA REGISTER 

This register is the user's window to the on-board full 
sector buffer. It contains the next byte of data to be 
written to or read from the internal sector buffer. 
When the DRQ (Data Request) line is asserted, the 
sector buffer contains data to be read during a Type II 
command, or is awaiting data to be written during a 
Type III command. If the WD1 002-05 is interfaced 
using programmed I/O, data transfers to this register 
can be implemented using programmed block 
moves. This register may not be read from or written 
to except in the context of a valid command. 

5.3 WD100205 ERROR REGISTER 

This Register contains specific fault information per- 
taining to the last command executed. This register 
is only valid if the error bit in the status register is set. 
The error register is read only. Table 5-2 shows the 
error register bits. 

Table 5-2= Error Register Bits 



DAM NOT FOUND 



Bit 


Error Register 


7 
6 
5 
4 
3 
2 
1 



Bad Block Detect 
Uncorrectable Error 
CRC Error ID Field 
ID Not Found 

Aborted Command 
TROOO Error 
DAM not found 



TROOO ERROR 



ABORTED 
COMMAND 



ID NOT FOUND 



Will be set during a read sector 
command if, after successfully 
identifying the ID field, the data 
address mark was not detected 
within 16 bytes of ID field. 

Will be set during a restore 
command if the track 000 line 
was not asserted by the drive 
after all stepping pulses have 
been issued. The Winchesters 
are issued a maximum of 1023 
stepping pulses and the flop- 
pies, a maximum of 256 
stepping pulses. 

Indicates that a valid command 
has been received that cannot 
be executed based on status 
information from the drive, i.e. 
drive not ready, seek complete 
not asserted, or write fault. 
Interrogation of the status 
register by the host may be per- 
formed to determine the cause 
of this failure. 

When set, this bit indicates that 
an ID field containing a speci- 
fied cylinder, head, sector 
number, or sector size was not 
found after all the retries have 
been executed. 



5-1 



UNCORRECTABLE 
ERROR 



BAD BLOCK 
DETECT 



Indicates that an ECC or CRC 
error was encountered in a data 
field during a read sector com- 
mand and the error was uncor- 
rectable. 

Indicates that a bad block mark 
has been detected in the speci- 
fied ID field. If the command 
issued was a write sector com- 
mand, write gate may be pulsed 
but the sector will not be 
written if generated from a read 
sector command, the data field 
will not be read. Note that bad 
block may not be detected if 
there is a flaw in the ID field. 



5.4 DIAGNOSTIC ERRORS 

On power-up, or when specifically commanded to, 
the WD1002-05 will run a series of internal diagnostic 
tests. When an error is encountered, the diagnostic 
routine is terminated. A binary error code is set in the 
error register without the error bit of the status 
register being set. The diagnostic routines are 
exercised in the following order: 



Error Code 


Major Functional Failure 


5 


WD1015error 


4 


WD1014 or bus error 


3 


sector buffer error 


2 


WD1 010 error 


1 


WD2797 error 





Pass — WD1002-05 is functional 


.5 WRITE PRECOMP 



The write precompensation register holds the cyl- 
inder number where the RWC line will be asserted 
and write precompensation logic is to be turned on. 
This write-only register is loaded with the cylinder 
number divided-by-4 to achieve a range of 1024 cyl- 
inders. For example, if write precompensation is de- 
sired for cylinder 128 (80 Hex) and higher, this register 
must be loaded with 32 (20 Hex). The write precom- 
pensation delay is fixed at 12 nanoseconds from 
nominal. 

This register is not used for floppy disk drives. Floppy 
disk write precompensation is contained in WD2797 
and set as described in the "Summary of Adjustment 
Procedure" in SECTION 9 (MAINTENANCE) of this 
manual. 

5.6 SECTOR COUNT 

The sector count register is used in read sector, write 
sector, and format commands to implement multiple 



sector handling with one command. The value of zero 
implies a transfer of 256 sectors (any size). For read 
and write multiple sector commands, the sector 
count is decremented, and the sector number is in- 
cremented after each sector transfer to or from the 
buffer. During a format command, this register is 
loaded with the number of sectors to be formatted 
and decremented as each sector is formatted until it 
reaches zero. During format, sector numbers are 
specified using interleave tables loaded in the sector 
buffer. 

5.7 SECTOR NUMBER 

This register is loaded with the desired sector num- 
ber prior to a read or write command. The sector 
number register may be read or written to by the host. 

5.8 CYLINDER NUMBER 

These two registers form the cylinder number where 
the head is to be positioned on a seek, read, or write 
command. The two least significant bits of the cyl- 
inder high register form the most significant bits of 
the cylinder number as illustrated below: 



Cylinder High Cylinder Low 



7 


6 


5 


4 


3 


2 


1 
9 8 


7 
7 


6 
6 


5 
5 


4 
4 


3 
3 


2 
2 


1 
1 







Register bits: 
Cylinder bits: 



When bit of the cylinder high register (bit 8 of cyl- 
inder register) is set to a 1 during floppy operation, 48 
tpi disks can be used in 96 tpi disk drives for all 
commands. When this bit is set to 0, only 96 tpi disks 
can be used. 

5.9 SDH REGISTER 

This register contains the ECC/CRC sector size, drive 
select, and head select bits. The SDH register is a 
read/write register organized as shown in Tables 5-3 
through 5-7. 



5-2 



Table 5-3. SDH Register 

Bit 
Function 



7 


6 5 


4 3 


2 1 


CRC/ 
ECC 


Sec 
Size 


Drive 
Select 


Head/ 

Drive 

Select 



Table 5-4. SDH Bits 6 & 5 



Bit 
6 


Bit 
5 


Sector Size 





1 
1 



1 

1 


256 Bytes 

512 Bytes 

1024 Bytes 

128 Bytes 



Table 5-5. SDHBits4&3 



Bit 

4 


Bit 

3 


Drive Selected 
(decoded & latched) 




1 
1 



1 

1 


Drive Sel 1 
Drive Sel 2 
Drive Sel 3 
Floppy Dr Sel 



Table 5-6. SDH Bits 2, 1 & Hard Disk 


Bit 


Bit 


Bit 


Head Selected 


2 


1 





Hard Disk 











HeadO 








1 


Headl 





1 





Head 2 





1 


1 


Head 3 


1 








Head 4 


1 





1 


Head 5 


1 


1 





Head 6 


1 


1 


1 


Head 7 



The SDH register is used to select either the Win- 
chester or the floppy disk drives as implied by bits 3 
and 4 shown in Table 5-5. If either bit is set to zero, 
then one of the hard disks is selected, and Table 5-6 
is used to select one of eight heads. 

When bits 3 and 4 are both set to 1, then a floppy disk 
will be selected. Table 5-7 is used to select one of 
four drives with side select or 1 as shown. 

Whenever different drives are to be accessed, the 
SDH register must be updated by the host prior to a 
command being issued. 



Table 5-7. SDH Bits 2, 1 & Floppy Disk 


Bit 


Bit 


Bit 


Floppy Drive & 


2 


1 





Head Select 











FD1 — HSO 








1 


FD1 — HS1 





1 





FD2 — HSO 





1 


1 


FD2 — HS1 


1 








FD3 — HSO 


1 





1 


FD3 — HS1 


1 


1 





FD4 — HSO 


1 


1 


1 


FD4 — HS1 



5.10 STATUS REGISTER 

After execution of a command, the status register is 
loaded with status information pertaining to the com- 
mand executed. The host must read this register to 
ascertain successful execution of the command. The 
status register is a read-only register; it cannot be 
written to by the host. If the BUSY bit is set, no other 
bits in this register are valid. Accessing this register 
will cause the INTRQ line to be reset. 

Status register bits are shown in Table 5-8. 

Table 5-8. Status Register Bits 



Bit 


Status Register 


7 


Busy 


6 


Drive Ready 


5 


Write Fault 


4 


Seek Complete 


3 


Data Request 


2 


Corrected Data 


1 


Not used 





Error 



ERROR 



CORRECTED DATA 



When set, indicates that one or 
more bits are set in the error 
register. It provides an efficient 
means of checking for an error 
condition by the host. This bit is 
reset on receipt of a new 
command. 

This bit indicates that an error 
correction has been success- 
fully completed on the data 
field just read from the Win- 
chester disk. For multiple mode 
operations, this bit indicates 
one or more data fields have 
been successfully corrected. If 
an uncorrectable error occurs, 
the command is terminated 
with the appropriate bit being 
set in the error register. 



5-3 



DATA REQUEST 



SEEK COMPLETE 



WRITE FAULT/ 
WRITE PROTECT 



Functions the same as the DRQ 
line. When set, it indicates that 
the sector buffer is ready to ac- 
cept data or contains data to be 
read by the host. The data re- 
quest bit is reset when the 
sector buffer has been fully 
read or written. Normally, the 
host need not consult this bit to 
determine if a byte should be 
transferred. 

Indicates the condition of the 
seek complete line on the se- 
lected Winchester drive. For 
Floppy drives, this line is as- 
serted when the SDH register is 
reloaded. 

Indicates the condition of the 
write fault line on a selected 
Winchester drive. The WD1002- 
05 will not execute any com- 
mand if this bit is set. 

If a write-protected disk is 
sensed in a selected floppy 
drive during a write operation, 
the write fault bit will be set. 
The command will then be a- 
borted and no writing will take 
place. 



READY Indicates condition of ready 

line on drive. WD1002-05 will 
not execute any commands un- 
less the ready bit is set. Normal- 
ly this line is asserted for 
Floppy drives when the SDH 
register selects any floppy 
drive. A user available jumper 
option can be implemented if 
the READY line is available 
from the floppy drive. 

BUSY After issuing a command, or 

initialing WD1002-05 internal 
diagnostics, this bit will be set 
indicating that the WD1 002-05 
is busy executing a command. 
No other bits or registers are 
valid when this bit is set. 

5.11 COMMAND REGISTER 

All commands are loaded into this register after the 
task files have been set. Writing to this register will 
cause the INTRQ Line to be reset. The command reg- 
ister is a write-only register. Refer to SECTION 6 
(COMMANDS), subsection 6.1 for further details. 



5-4 



SECTION 6 
COMMANDS 



6.1 GENERAL 

The WD1 002-05 executes six, easy-to-use, macro 
commands. Most commands feature automatic "im- 
nijc»H" cckoif Mfhj§h maanc the host s x/ stem need not 
tell the WD1 002-05 where the R/W heads of each 
drive are nor when to move them. The controller auto- 
matically performs all retries on errors encountered, 
including data ECC errors. If the R/W head mis-posi- 
tions, the WD1 002-05 will automatically perform a 
restore and a re-seek. If the error is completely unre- 
coverable, the WD1002-05 will simulate a normal 
completion to simplify the host's software. 

The commands executed by the WD1 002-05 are 
mapped to the commands supported by the two disk 
controllers. The format of the WD1 002-05 commands 
is the same as that of the WD1010 commands. The 
onboard WD1015 buffer manager translates this for- 
mat for the WD2797, transparent to the user. Error cor- 
rection and the Long modes are only supported for 
the Winchester Disk Controller, therefore the host 
must set SDH bit 7 = and L = for all the 
commands when a floppy disk is selected. 

Commands are executed by loading the command 
byte into the command register while the controller 
is not busy. The host must observe the following 
simple protocol: 

• The task file must be loaded prior to issuing a 
command. Only parameters that change from the 
previous command need be entered. 

• For any write/format operations, the sector buffer 
must be filled with the appropriate data before the 
command can be executed by the WD1 002-05. 

No command will execute if the seek complete or 
ready lines are false, or the write fault line is true. 
Normally it is not necessary to poll these signals be- 
fore issuing a command. If the WD1002-05 receives a 
command that is not defined in Table 6-1, undefined 
results will occur. 

6.2 WD1002-05 COMMAND SUMMARY 

Commands have been divided into three types as 
summarized in Table 6-1 . 



Table 6-1 . Command Types 



TYPE 


COMMAND 


BITS 
7 6 5 4 3 2 10 




Test 


10 10 




Restore 


n O n 1 rn rn rn m 

~ - ~ -o '£. ' I '\J 




Seek 


1 1 1 r3 X2 n rrj 


II 


Read Sector 


1 D M L 


III 


Write Sector 


1 1 M L 


III 


Format Track 


10 10 



L = Long bit : = normal mode 
M = Multiple sect : = Single sector 
D = read interrupt: = Programmed I/O Mode 

1 = Long mode 
1 = Multiple sector 
1 = DMA Mode 

6.2.1 STEPPING RATES 



Table 6-2. 13-10 — Stepping Rate 


r3-m 


Winchester Disk Drives 


Floppy Disk Drives 


0000 


~35/js 


~15^s 


0001 


0.5 ms 


1.0 ms 


0010 


1.0 ms 


2.0 ms 


0011 


1.5 ms 


3.0 ms 


0100 


2.0 ms 


4.0 ms 


0101 


2.5 ms 


5.0 ms 


0110 


3.0 ms 


6.0 ms 


0111 


3.5 ms 


8.0 ms 


1000 


4.0 ms 


10 ms 


1001 


4.5 ms 


12 ms 


1010 


5.0 ms 


14 ms 


1011 


5.5 ms 


16 ms 


1100 


6.0 ms 


18 ms 


1101 


6.5 ms 


20 ms 


1110 


7.0 ms 


25 ms 


1111 


7.5 ms 


40 ms 



6-1 



6.3 TYPE I COMMANDS 

Type I commands do not effect transfer of data be- 
tween the host and the WD1 002-05 but merely posi- 
tion the R/W heads of the selected drive or run 
diagnostics. The restore and seek commands have 
explicit stepping rate fields. The lower four bits of 
these commands form the stepping rate for the 
drives. 

6.3.1 TEST COMMAND 

Bit code : 1 1 

The test command is used to run internal diagnostics 
for checking WD1002-05 board function. It is mainly 
employed to isolate faults in the board logic. This 
command is always executed on a MR strobe. Any 
faults are reported as error codes. (See Section 5.4 for 
a description of the error codes.) 

6.3.2 RESTORE 

Bit code :0 1 R3 R2 R1 R0 

The restore command is used to calibrate the posi- 
tion of the R/W head on each drive by stepping the 
head outward until the TR000 line goes true. Upon re- 
ceipt of the restore command, the BUSY bit in the 
status register is set. Cylinder high and cylinder low 
registers are cleared. For Winchester operation, the 
actual stepping rate is determined by the Seek Com- 
plete period. For Floppy operation, a minimum step- 
ping pulse of 8 msec, is used. However, the stepping 
rate field specified by the host is saved internally for 
use in all future implied seeks. The state of seek 
complete, ready and write fault are sampled, and if an 
error condition exists, the aborted command bit in 
the error register is set, the error bit in the status reg- 
ister is set, an interrupt is generated, and the BUSY 
bit is cleared. 

Regardless of errors encountered, the internal head 
position register for the selected drive is cleared. The 
TR000 line is sampled. If TR000 is true, an interrupt is 
generated and the BUSY bit is reset. If TR000 is not 
true, stepping pulses at a rate determined by the 
stepping rate field are issued until the TR000 line is 
activated. When TR000 is activated, the busy bit is 
reset and interrupt is issued. If the TR000 line is not 
activated within 1024 stepping pulses, the TR000 
error bit in the error register and the error bit in the 
status register are set, the BUSY bit is reset, and an 
interrupt is issued. 



6.3.3 SEEK 

Bit code : 1 1 



1 R3 R2 R1 R0 



The seek command positions the R/W head at a cer- 
tain cylinder. It is primarily used to start two or more 
concurrent seeks on drives that support buffered 
stepping. Note that the seek complete line is not 
sampled after the seek command so that multiple 
seek operations may be started using drives with 
buffered seek capability. 

6.4 TYPE II COMMANDS 

Type II commands characteristically transfer blocks 
of data from the WD1 002-05 buffer to the host. This 
type of command has an implicit stepping rate as set 
by the last restore or seek command. 

6.4.1 READ SECTOR 

Bit code :0 1 D M 

The read sector command is used to enable the host 
computer to read a sector of data from the disk. If 
ECC is enabled, ECC bytes are recomputed by the 
WD1002-05. After the buffer is full, the recorded ECC 
bytes are compared to the recomputed check bytes 
to generate the syndrome bytes. If the syndrome is 
non-zero, errors have occurred. Error correction is 
invoked by the WD1015 if two consecutive syn- 
dromes match, otherwise a maximum of 8 retries is 
attempted by the WD1015. If the data is correctable, 
the WD1015 makes the correction and passes the 
data in the buffer to the host. If, after eight retries, the 
syndromes do not match, the WD1 002-05 sends an 
error status to the host along with the status from the 
WD1010. Multiple sector read commands are modi- 
fied to single sector commands and are issued a mul- 
tiple number of times. The status and error registers 
are updated for every block of data transferred. 

During a Floppy read sector operation only CRC is 
used with the data fields. If a CRC error occurs in the 
data field, the WD1015 buffer manager attempts a 
maximum of 8 retries and reports the error only if it 
persists. Regardless of the drive accessed (Winches- 
ter or Floppy), CRC is used on all ID fields. 

6.4.1.1 READLONG Command 

Bit code :0 1 D M 1 

This command is similar to the read sector command 
except that the ECC operation producing the syn- 
drome is inhibited in the WD1002-05. Instead, the 
WD1 002-05 copies the four recorded check bytes 
from the disk and passes them unaltered to the host. 
This command is useful in debugging and verifying 
the ECC hardware and software. To do this, first write 



6-2 



normally and then issue the READLONG command. 
The data, or the check bytes may now be altered by 
the host and written to the disk using the WRITE- 
LONG command. If a read command is now issued, 
the WD1 002-05 will correct it as long as the error in- 
duced is within the correction capability of the ECC 
polynomial. This mode is not supported for floppy 
disk. 

6.4.1.2 DMA Read 

D = DMA Read Mode 



6.5.1 WRITE SECTOR 

Bit code :0 110 



MOO 



= Programmed I/O mode 

1 = DMA Mode 



The DMA bit is used to position INTRQ in relation to 
DRQs during the read sector command. If the DMA 
bit is reset (D = 0), the interrupt will occur along with 
the DRQ. This allows the programmed I/O host to in- 
tervene and transfer the data from the sector buffer. 
For programmed I/O, multiple transfer is not per- 
mitted (M = 0). If the DMA bit is set (D = 1), then the 
interrupt will occur only after the system DMA con- 
troller has transferred the entire buffer of data. This 
mode is always used with multiple sector transfers. 

6.4.1.3 Normal Completion 

A normal completion occurs when the WD1 002-05 en- 
counters no errors. The BUSY bit is reset. The status 
of the DMA bit in the command byte is examined. If 
this bit is reset (D = 0; programmed I/O mode), an in- 
terrupt is issued at this time. DRQ is set until all 
bytes of data have been read from the buffer. (Note: It 
is recommended that programmed I/O transfers 
should take place as a block move without consult- 
ing the DRQ bit in the Status Register.) After all the 
data has been moved from the buffer, the DMA bit in 
the command byte is consulted again. If this bit is set 
(D = 1; DMA mode) then an interrupt will be issued. 

6.5 TYPE III COMMANDS 

This type of command is characterized by a transfer 
of a block of data from the host to the WD1 002-05 buf- 
fer. These commands have implicit stepping rates as 
set by the last restore or seek command. 

The command wili not be executed by the WD1002-05 
controller unless the buffer has been completely 
filled by the host. 



The Write Sector command is used to write a sector 
of data from the host computer to the disk. Upon re- 
ceipt of the write command, the controller sets DRQ 
until the entire sector length of data has been written 
into the buffer. (Note: It is recommended that pro- 
grammed I/O transfers should take place as a block 
move without consulting the DRQ bit in the Status 
Register.) 

6.5.1.1 WRITELONG Command 

Bit code :0 1 1 M 1 

The WRITELONG command functions similarly to 
the write sector command except that the ECC oper- 
ation that computes the ECC word is inhibited in the 
WD1 002-05. Instead, the WD1 002-05 accepts a 4-byte 
appendage from the host and passes it unaltered to 
be written on the disc at the end of the data as check 
bytes. This mode is not supported for the floppy 
discs. 

6.5.2 FORMAT TRACK 

Bit code :0 10 10 

The format command is used for initializing the ID 
and data fields on a particular disk. Upon receipt of 
the format command, the controller sets the DRQ for 
the interleave table to be written to the buffer. In all 
cases, the number of bytes transferred to the buffer 
must correspond to the current sector size. 

When the buffer has been completely filled, the 
specified number of sectors are written and the DRQ 
is reset. The data field is written with 00 for the hard 
disks and E5 (hex) for the floppies. ECC or CRC bytes 
are automatically computed and written. 

Once the index is found, a number of ID and data 
fields are written to the disk. As each sector is writ- 
ten, the sector count register is decremented and 
consequently must be updated before each format 
operation. 



6-3 



PROGRAMMING 



7.1 GENERAL 

Users will find programming the WD1 002-05 relatively 
simple as a substantial amount of intelligence for- 
merly reauired bv host computers has been inconoor- 
ated 'into the WD1002-05 board. 

Thg VVD1QQ2-05 performs a!! needed retries even on 
head positioning errors. If there is an error in the data 
field, the WD1 002-05 will attempt to correct it 

Most commands feature automatic "implied" seek, 
which means that seek commands need not be is- 
sued to perform basic read/write functions. The 
WD1 002-05 keeps track of the head position up to 
eight read/write head assemblies, eliminating the 
need for the host system to maintain track tables. 

All transfers to and from disk are through an on-board 
sector buffer. This means that data transfers are fully 
interruptable and can take place at any speed that is 
convenient to the system designer. In the event of an 
unrecoverable error, the WD1 002-02 simulates a 
normal completion so that special error recovery 
software is not needed. 

This section assumes that the user has read Section 
5 (Task File) and Section 6 (Commands). 

7.2 SETTING UP TASK FILES 

Before any of the six macro commands may be exe- 
cuted, a set of parameter registers called the task 
files must be set up. For most commands, this 
informs the WD1 002-05 of the exact location on the 
disk where the data involved in the transfer is located 
or will be placed. For a normal read or write sector 
operation, the sector number, the size/drive/head, the 
cylinder number, and the command registers (usually 
in that order) will be written. 

Note that although most of these registers are read- 
able as well as writable, they are normally are not 
read from. Read capability for them is provided, how- 
ever, so that error-reporting routines can determine 
physically where an error occurred without recalcu- 
lating the sector, head, and cylinder parameters. 

Since all the task file parameters can be recalled by 
the WD1002-05, it is recommended that task file 
parameters be stored in the WD1 002-05 as they are 
calculated. This will save the programmer a few in- 
structions and microseconds by not maintaining two 
copies of the same information. 

7.2.1 CYLINDERS AND TRACKS 

Since most hard-disk drives contain more than one 
head per positioner, it is more efficient to step the 
R/W head assemblies of most disk drives by cyl- 
inders, not tracks, In other words, the disk driver soft- 



ware should be designed to read or write all data that 
is directly accessible by all the heads on a positioner 
before stepping to a new cylinder. Table 7-1 presents 
a cylinder-by-cylinder sequential file read on a four 
head, two-piatter disk drive. 



Table 7-1 . File Read on 4-Kead, 2-P latter Disk Drive 


Physical 
Cylinder 


Logical 

Head 

Number 


Physical 
Head Side 


Physical 
Platter 


25 
26 


3 



Top 
Bottom 


B 
A 


26 
26 


1 
2 


Top 
Bottom 


A 
B 


26 
27 


3 



Top 
Bottom 


B 
A 



7.3 TYPE I COMMAND PROGRAMMING 

Test, Restore and seek are Type I commands that 
position the R/W heads of the selected drive and set 
the implied stepping-rate register. No data is 
transferred to or from the data register. To execute a 
Type I command, the system software must perform 
the following functions in the order shown: 

1. Set up task file and issue command with stepping 
rate (WD1002-05 will attempt to execute Type I 
command) 

2. Wait for interrupt or for BUSY bit in status register 
to be reset 

3. Check error bit in status register for proper 
completion 

7.3.1 USE OF BUSY BIT 

Smaller, single-user systems can sense the comple- 
tion of a command by polling the BUSY bit of the 
status register. This bit (bit 7) is set whenever the con- 
troller starts a disk operation or internal diagnostics, 
and is reset whenever the controller is ready to com- 
municate with the host computer. 

On the WD1 002-05, the BUSY bit is located in the 
same place as the sign bit of many computers to sim- 
plify the polling process. 

One way to poll this bit using 8080 code is as follows: 

WAIT: IN STATUS ; I nputWDI 002-05 

Status register 

ANA A ;Update 8080 sign 

flag 

JM WAIT ;Wait if BUSY (sign) 

bit set 



7-1 



This is another way to poll the BUSY bit using PDP-1 1 
code: 

WAIT: MOVB @#STATUS,R0 ;lnput status, 

update sign flag 
BMI WAIT ;Wait if BUSY (N) bit 

set 

7.3.2 USE OF INTERRUPTS 

Another, more efficient way of notifying the CPU that 
the WD1002-05 has completed a command is through 
interrupts. The INTRQ line on the WD1002-05 makes 
a low to high transition whenever the disk controller 
requires CPU intervention. This allows the host CPU 
to run other tasks while the WD1002-05 is reading or 
writing data to the disk. 

7.3.3 USE OF THE ERROR BIT 

As the WD1002-05 simulates normal completions 
when errors have been encountered, the only way to 
determine error status is to check the error bit in the 
status register. The WD1 002-05 error bit is so located 
that it can be easily tested by rotating it into the carry 
bit of many processors. The contents of the error reg- 
ister are not valid unless the error bit is set. 

One way to check the Error bit using 8080 code is as 
follows: 



IN 



STATUS 



RAR 



;Get status (if not 
already in A) 
; Rotate error bit 
intoC 
JC ERROR ;Jump if error found 

In certain hardware configurations, the following can 
check the error bit using PDP-11 code: 

BIT @#STATUS,#1 ;Bit test the error bit 
BNE ERROR ; Branch if error 

found 

7.3.4 USE OF THE CORRECTED BIT 

Correctable errors are usually quite benign and can 
almost always be ignored. Some systems designers, 
however may wish to log their occurrence. The cor- 
rected bit has been placed in the status register to 
facilitate error logging. Correctable and fatal errors 
can be detected with the following 8080 code: 



IN STATUS 

ANI 5 

JNZ SOMERR 



;GetWD1002-05 
status 

; Mask off Error and 
Correct bits 
;Jump if we have 
either a 

jcorrectable or fatal 
error 



7.4 TYPE II COMMAND PROGRAMMING 

The only Type II command is the read sector com- 
mand. This command is characterized by the transfer 
of a block of data from the WD1 002-05 buffer to the 
host. The command features implied seek with an 
implicit stepping rate. To execute a Type II single- 
sector command in programmed I/O mode, the sys- 
tem software must perform the following functions 
in the order shown: 

1. Set up task file and issue command with DMA bit 
reset (WD1002-05 will attempt to read sector) 

2. Wait for interrupt or for BUSY bit in status register 
to be reset 

3. Perform a block move from WD1 002-05 buffer to 
system memory 

4. Check error bit in status register for proper 
completion 

Note: Steps 3 and 4 above can be reversed. 

To execute a Type II single or multiple sector com- 
mand in DMA mode with interrupts, the system soft- 
ware does the following: 

1. Set up task file and issue command with DMA bit 
set 

2. Set up DMA controller (WD1 002-05 will attempt to 
read single or multiple sectors) (DMA controller 
will move data from WD1 002-05 to memory) 

3. Wait for interrupt from WD1 002-05 

4. Check error bit in status register for proper 
completion 

Note: The above sequence is preferred, but steps 1 
and 2 above can be reversed. 

7.4.1 DMA MODE 

The DMA mode bit (D) in the foregoing read sector ex- 
amples is a special bit in the command byte used to 
optimize the WD1002-05 interrupts during pro- 
grammed I/O and DMA operations. If the DMA bit is 
reset (D = 0), the interrupt will come before the buffer 
is transferred. This allows a programmed I/O host to 
intervene and transfer the buffer of data. If the DMA 
bit is set (D = 1), then the interrupt will occur only 
after the data has been transferred. This allows the 
host to go uninterrupted until the entire buffer has 
been transferred. 

7.4.2 BLOCK MOVES 

The WD1002-05 performs all transfers between itself 
and the disk drive through an on-board full sector buf- 
fer. Once the disk has been read, the data is available 
to the host at any rate from DC to as high as a byte 



7-2 



every 500 ns. In programmed I/O applications there is 
no need to consult the DRQ bit in the status register 
to determine if another byte is ready to be processed. 
Once an interrupt occurs or the BUSY bit is reset on a 
read, the host computer should do a block move of 
all the bytes in the sector. 

The following 8080 code demonstrates a transfer 
from the WD1 002-05 to system memory. The transfer 
address is in HL and the byte count is in B: 



READIT: IN 



DATA 



MOV M,A 

INX H 

DCR B 

JNZ READIT 



;Get data from 

WD1 002-05 sector 

buffer 

;Store it in memory 

; Increment memory 

pointer 

; Decrement byte 

counter 

;Do it again if whole 

sector not xferred 

The following Z-80 instruction does it all. The transfer 
address is in HL, byte count is in B and WD1002-05 
data register address in C: 

READIT: INIR ;Transfer buffer 

from WD1 002-05 to 
memory 

7.4.3 USING DMA 

A special bit in the read sector command optimizes 
the WD1002-05 in terrupts for DMA operation. 

7.4.4 MULTIPLE SECTOR TRANSFERS 

The WD1 002-05 can transfer more than one sector 
per command, if interfaced, using DMA and inter- 
rupts. Transfers as large as an entire track can be exe- 
cuted. The sector count register holds the number of 
records to be transferred (if sector count is zero, then 
256 records will be transferred.) The sector number 
register holds the starting sector of the transfer. 
When a multiple sector transfer is successfully 
completed, the sector count register will be equal to 
zero and the sector number register will be equal to 
the last sector transferred plus one. 

If a fatal error is encountered during a multiple sector 
transfer, the sector number register will be left point- 
ing to the sector that contained the fatal error, and 
the sector count register will hold the number of sec- 
tors that were not transferred. 

If a correctable error is encountered during a multiple 
sector read, the corrected bit in the status register 
will be set, but the operation will not be terminated 
because correctable errors are not considered fatal. 



7.4.4.1 Partial Sector Transfers 

The WDi 002-05 permits partial sector transfers on 
read operations. This allows the user to read the first 
part of a sector and discard the rest. During pro- 
grammed I/O, the byte counter in the block move 
routine is set to the number of bytes to be read. 
During DMA operations, the DMA controller is set 
with the number of bytes to be transferred. 

Normally, during a DMA read operation, the 
WD1 002-05 interrupts the host after a sector has 
been transferred. However, if only a partial sector is 
being read, the WD1 002-05 does not know that the 
operation has been completed. Therefore, the 'trans- 
fer complete' interrupt must come from the DMA 
controller. 

During write sector operations, the DMA controller 
will interrupt the system after the buffer has been 
transferred to the WD1 002-05, but before the data 
have been written. Some systems with advanced in- 
terrupt handling capabilities can easily mask off this 
spurious DMA interrupt. For those systems that can- 
not, the WD1002-05 has a provision built into its 
command structure to detect read operations. 

7.4.4.2 Interrupt Source Selection 

Bit 4 of all commands determines whether the opera- 
tion will be a read sector operation or something 
else. Those commands that require the interrupt from 
the WD1002-05 have this bit set to 1. The read sector 
command (the only one that might need the DMA 
controller's interrupt) has this bit set to a 0. Bit 3 of 
the command is then used to select either 
programmed I/O interrupts or DMA type interrupts. 

7.4.4.3 Clearing Hardware DRQ 

During partial sector reads, the DMA controller will 
stop the DMA transfer before the WD1 002-05 has a 
chance to issue its last data request. Because of this, 
the DRQ line might be set the next time transfer pa- 
rameters are sent to the DMA controller. To avoid 
spurious (and often fatal) DRQs, the user must do a 
hardware clear of the DRQ line unless another com- 
mand is issued. DRQ is actually cleared by doing 
dummy reads of the data register to dump the rest of 
the data. 

7.4.4.4 Interrupt Selection Circuit 

If the user is reading partial sectors with the 
WD1 002-05 and wants to have the system automati- 
cally configure its interrupts, a circuit similar to that 
shown by Figure 7-1 will have to be implemented. 



7-3 



WD1002 
INTRQ >- 



MR 



DAL4 >- 



CS >- 
WE >- 
AO >- 



DMA >- 

INTRQ 



-Q X 



~ s _ 



=r^ 





SYSTEM 
INTRQ 



Figure 7-1 . Interrupt Selection Circuit 



7.4.5 SIMULATED COMPLETIONS 

All WD1 002-05 commands (except multiple sector 
transfers) act in precisely the same manner, whether 
or not an error was encountered. The only way to de- 
termine whether an error has occurred is to sample 
the error bit in the status register. Simulated comple- 
tions offer the system designer the following tangi- 
ble benefits: 

• Simplifies masking and generation of interrupts 

• Simplifies non-error handling portions of the 
system software 

• Eliminates the software overhead of handling 
different types of errors 

• Simplifies system software error handling 
validation (any error is handled the same way as 
any other error) 

• Prevents system failure in the event of some 
obscure error condition that the system program- 
mer did not anticipate 

7.5 TYPE III COMMAND PROGRAMMING 

Write sector and format are Type III commands. 
These commands are characterized by the transfer of 
a block of data from the host to the WD1 002-05 buffer. 
Like the Type II commands, these commands feature 
implied seek with an implicit stepping rate. To exe- 
cute a single sector Type III command in pro- 
grammed I/O mode, the system software must go 
through the following functions in the order 
indicated: 

1. Set up task file and issue command 

2. Perform block move from system memory to 
WD1002-05 buffer (WD1 002-05 will attempt to write 
a sector or format) 



3. Wait for interrupt or for BUSY bit in status register 
to be reset 

4. Check error bit in status register for proper 
completion 

To execute a single or multiple sector Type III com- 
mand in DMA mode with interrupts, the system soft- 
ware goes through the following steps: 

1 . Set up task file and issue command 

2. Set up DMA controller (DMA controller will move 
data from memory to WD1 002-05) (WD1 002-05 will 
attempt to write sector or format) 

3. Wait for interrupt from WD1 002-05 

4. Check error bit in status register for proper 
completion 

Note: Steps 1 and 2 above can be reversed. 

7.5.1 FORMATTING 

The format command is very similar to the write sec- 
tor command, except that the sector buffer is filled 
with interleave and bad block information instead of 
with user data. Two bytes will be written to the buffer 
for each sector to be formatted. 

The first (lower) byte will be either a 00 or an 80 in hex. 
If the lower byte is a 00, the sector is marked as good. 
If the lower byte is an 80, and there is any attempt to 
read it or write to it, the sector will set the bad block 
bit in the status register. See cautions regarding 
media imperfections mapping in subsection 7.5 Bad 
Block Mapping. 

The second (upper) byte is the logical sector number 
of the next sector to be formatted. This number will 
be recorded on the disk. The sector number register 
is not used during format. 



74 



On a 32-sector-per-track disk, 32 pairs of bytes con- 
taining formatting information must be supplied to 
the drive during each format operation. To start the 
format operation, the buffer must be completely 
filled, even if the sector table is not as long as the 
buffer. This means that on a 32-sector-per-track disk, 
with 64 bytes of formatting information supplied, if 
the sector size is 256 bytes, then 192 bytes of gar- 
bage must be passed to the controller to start the for- 
mat operation. 

As the contents of the sector buffer do not imply how 
many sectors are to be formatted, a dedicated reg- 
ister is provided. This Sector Count register must be 
loaded with the number of sectors to be formatted 
before every format operation. To calculate the maxi- 
mum number of sectors per track, see Appendix C. 

7.5.2 INTERLEAVING 

If sequential sectors on the disk are to be read, the 
next sector will pass by the read/write head before a 
read or write can be set up. The disk will then have to 
make a complete rotation to pick up this next sector. 
If an attempt is made to read all 32 sectors on a parti- 
cular track, it requires 32 rotations or about a halka 
second per 8K bytes. This performance can be sig- 
nificantly improved by interleaving, a technique that 
allows the system to read or write more than one 
sector per rotation. 

Suppose the system takes less than three sector 
times (3 times 32 rotational periods with 256 byte sec- 
tors) to digest the data that it has read and to set up 
the next read operation. This means that if the sec- 
ond logical sector can be physically placed four sec- 
tors away from the first one, the controller will be 
able to read it without much delay. This four-to-one in- 
terleave factor will allow a potential reading of the en- 
tire track in only four rotations. In the example given, 
the throughput will be increased by a factor of eight. 

The simplest way to determine the optimum inter- 
leave for any particular system is through experi- 
mentation. If the system maintains its directories or 
virtual memory-swapping areas in a certain place on 
the disk, it sometimes makes sense to have more 
than one interleave. 

To simplify driver software, the WD1002-05 will auto- 
matically map logical sectors to physical sectors to 
achieve interleave. This logical-to-physical map is re- 
corded during the format operation on each track of 
the disk in the ID fields of the sectors. Table 7-2 is an 
example of an interleave table for a 32-sector track 
with 4:1 interleave and no bad blocks. 



The first byte in each byte-pair in Table 7-2 is set to 00. 
This marks each block as a "good" block. The sec- 
ond byte of each byte-pair is the logical sector num- 
ber. The first byte pair in Table 7-2 represents the first 
logical sector of the track. The underlined byte pair 
represents the second logical sector. 

7.6 BAD BLOCK MAPPING 

Winchester and thin-film-technology drives often do 
not have perfect media Manufacturers allow imper- 
fections in the media to reduce cost which conse- 
quently lowers the cost of drives. 

The user of the WD1002-05 which interfaces with 
Winchester and thin-film-technology drives is re- 
quired to map out any media imperfections. This can 
be accomplished in various ways, some highly oper- 
ating-system dependent. Here are a few ideas: 

7.6.1 SECTOR PRE-ALLOCATION 

If the operating system supports random sector or 
group allocation, the bad blocks can sometimes be 
mapped out by recording an un-deletable file, using 
all the bad sectors on the disk. When the operating 
system tries to write to the bad block, it will see that 
the sector or group that contains the error has al- 
ready been allocated. The operating system will auto- 
matically map over the bad sector. 

There are some minor restrictions associated with 
this form of bad-block mapping: the file that contains 
the bad sector must never be moved to another sec- 
tion of the disk, the bad sector file may not be read 
(for obvious reasons), and reads or writes to the disk 
that do not consult the disk allocation map (physical 
reads/writes) are not allowed. 

Table 7-2. Interleave Table with 32 Sectors and 
4:1 Interleave 



00 


00 


00 


08 


00 


10 


00 


18 


00 


01 


00 


09 


00 


11 


00 


19 


00 


02 


00 


0A 


00 


12 


00 


1A 


00 


03 


00 


0B 


00 


13 


00 


1B 


00 


04 


00 


0C 


00 


14 


00 


1C 


00 


05 


00 


0D 


00 


15 


00 


1D 


00 


06 


00 


0E 


00 


16 


00 


1E 


00 


07 


00 


OF 


00 


17 


00 


1F 



Note: The balance of the buffer must be filled with 
something to start the format operation. 



7-5 



7.6.2 ALTERNATE TRACKS 

The alternate-track method works on most operating 
systems but requires more software overhead. When- 

owor a raari r\r u/rito i<j attomntoH tho trarrk numhpr 

(cylinder and head select) is checked against a table 
maintained by the operating system or driver. If the 
track number matches the table, the driver knows 
that there is a flaw somewhere on that track and 
looks up the alternate track for the flawed one. The 
read or write is then performed elsewhere. 

The primary disadvantage of this type of bad-block 
mapping is the high software overhead. When the 
system is brought up, the alternate-track table has to 
be read from a flawless area of the disk. After it has 
been read, every read or write operation must check 
the alternate-track table before performing its respec- 
tive operation. 

7.6.3 SPARE SECTORS 

The spare-sector method is probably the simplest to 
implement in most systems. Its primary disadvan- 
tage is that at least one sector must be set aside as a 
spare for each track. During format, the physical sec- 
tor that contains the flaw is written with some illegal 
sector number. The physical sector following it con- 
tains the real logical sector and its data. Table 7-3 is 
an interleave table that shows how the user mapped 
out the fifth physical sector by telling the WD1002-05 
to write a logical sector number of FF to it. 

Table 7-3. Interleave Table with 32 Sectors and 
4:1 Interleave — Physical Sector Five 
Mapped Out 



00 


00 


00 


08 


00 


10 


00 


18 


00 


FF 


00 


01 


00 


09 


00 


11 


00 


19 


00 


02 


00 


0A 


00 


12 


00 


1A 


00 


03 


00 


0B 


00 


13 


00 


1B 


00 


04 


00 


OC 


00 


14 


00 


1C 


00 


05 


00 


0D 


00 


15 


00 


1D 


00 


06 


00 


0E 


00 


16 


00 


1E 


00 


07 


00 


OF 


00 


17 



Please note that when formatting the disk in this 
manner, at least one sector must have an illegal sec- 
tor number. Also, as one sector has been allocated to 
bad block mapping, a sector 1 F no longer exists. 

7.6.4 BAD BLOCK BIT 

The WD1 002-05 allows the user to set a marker that is 
recorded into the ID field. When the WD1002-05 at- 
tempts to read or write a sector with a bad-block mark 
set, the operation will be aborted and the error bit in 
the status register and the bad-block bit in the error 
register will be set. The size, head, cylinder, sector 
and ID CRC fields of the selected sector must be 
correct in order to detect a bad-block mark. This 
means the ID field must be error-free in order to de- 
tect the bad block mark. 

Table 7-4 shows an interleave table where the 
user has marked all the sectors with a bad-block 
mark and recorded all sectors redundantly. The 
interleave is not very important here, because it is 
assumed that the driver will not attempt to read bad 
sectors sequentially. 

Table 7-4. Interleave Table with Redundant Sectors, 
No Interleave, and All Sectors Marked as 
Bad Blocks 



80 


00 


80 


01 


80 


02 


80 


03 


80 


04 


80 


05 


80 


06 


80 


07 


80 


08 


80 


09 


80 


0A 


80 


0B 


80 


OC 


80 


0D 


80 


0E 


80 


OF 


80 


10 


80 


11 


80 


12 


80 


13 


80 


14 


80 


15 


80 


16 


80 


17 


80 


18 


80 


19 


80 


1A 


80 


1B 


80 


1C 


80 


1D 


80 


1E 


80 


1F 


80 


00 


80 


01 


80 


02 


80 


03 


80 


04 


80 


05 


80 


06 


80 


07 


80 


08 


80 


09 


80 


0A 


80 


0B 


80 


0C 


80 


0D 


80 


0E 


80 


OF 


80 


10 


80 


11 


80 


12 


80 


13 


80 


14 


80 


15 


80 


16 


80 


17 


80 


18 


80 


19 


80 


1A 


80 


1B 


80 


1C 


80 


1D 


80 


1E 


80 


1F 



7-6 



SECTION 8 
THEORY OF OPERATION 



8.1 GENERAL 

The WD1002-05 Winchester Floppy Disc Controller 
(WFC) is a stand-alone general purpose controller 
board designed to provide a buffer interface between 
a host controller and a combination of up to three 
Winchester disc drives and four floppy disk drives. 
The WD1002-05 is fabricated using a proprietary chip 
set designed specifically for Winchester Floppy disc 
control. 

The design of the WD1002-05 circuitry implements all 
of the logic required for host interface, WD1002-05 in- 
ternal diagnostics, variable length sector buffer, task 
files, ECC diagnostics and correction, data separa- 
tion, and WD1 002-05 control. The Winchester drive 
signals from the host controller are based upon the 
floppy look-alike interface with the Seagate Tech- 
nology ST506 and other compatible drives. All neces- 
sary drive signal decoding for the floppy disc drives 
is performed solely by the WD1 002-05 so that the 
host controller sees only Winchester drive signal 
format. 

8.2 WD1002-05 ARCHITECTURE AND 
FUNCTIONAL DESCRIPTION 

The internal structure of the WD1002-05, illustrated in 
Figure 8-1, consists of six major functional blocks as 
well as all necessary support logic. They are as 
follows: 

1. Host Interface Logic (HIL) 

2. Buffer Manager Control Processor (CP) 

3. Error Detection and Support Logic (EDS) 

4. Sector Buffer (SB) 

5. Winchester Disc Drive and Buffer Interface (WDBI) 

6. Floppy Disc Drive and Buffer Interface (FDBI) 

The host can communicate with the Winchester or 
floppy disc via the J5B. On power-up, the host is 
required to strobe MR which in turn causes the 
WD1 002-05 to execute a special TEST command that 
initiates internal diagnostic routines within the 
WD1002-05 to ensure the functionality of the 
WD1002-05. The internal diagnostic routines can also 
be exercised by the host explicitly, in addition to five 
other macro commands used to execute disk opera- 
tions. The six macro commands are as follows: 

1. TEST 

2. RESTORE 

3. SEEK 

4. READ 

5. WRITE 

6. FORMAT 



Prior to issuing any command to the WD1 002-05, the 
host must first set up command parameters in the 
task file registers, i.e. sector size, drive select infor- 
mation, sector number accessed, etc. The host must 
then fill the sector buffer with the required data if 
either a WRITE or FORMAT command is to be exe- 
cuted by the WD1 002-05. The WD1 002-05 BUSY 
status bit is set when the sector buffer has been 
filled by the host, or immediately upon receipt of 
any other type of command from the host. The 
WD1 002-05 then executes the command issued, at 
which time all communications between the host 
and the WD1 002-05 are suspended. The only access 
available to the host is the ability to poll the status of 
the BUSY bit. The command issued by the host is 
read by the CP from the command register in the task 
file, interpreted, and re-issued to either the Win- 
chester or floppy disk processor, or executed directly 
by the CP. Upon completion of the command, the 
WD1 002-05 sets the INTRQ/DRQ lines, dependant 
upon the type of command issued, and clears the 
BUSY bit. At this time, the host can read status and 
error information from the task files before issuing 
another command. 

8.2.1 HOST INTERFACE LOGIC (HIL) 

The HIL contains the requisite logic to buffer all data/ 
command access between the host, the WD1 002-05, 
the WD1010, and the WD2797 controllers. Bus proto- 
col is exactly the same as the WD1010 Hard Disc 
Controller device. All data and command information 
is transferred on an 8-bit DAL bus. This tristate asyn- 
chronous bus is controlled by the host, only if the 
WD1 002-05 is not BUSY. The host accesses the 
WD1002-05 by presenting a stable address (A0-A2) 
along with a RE or WE strobe qualified byCS. The di- 
rection of transfer is determined by the RE and WE 
signals. For DMA transfers, the WD1 002-05 provides 
a DRQ signal to inform the DMA controller of a pend- 
ing transfer. HIL also produced INTRQ for interrupts 
after commands, or to signal a transfer completion 
for Interrupt Driven Systems. The host may reset the 
WD1 002-05 by asserting MR (if MR is asserted, the 
WD1002-05 internal diagnostics routine is initiated 
and the host must wait for BUSY to be cleared before 
issuing a command to the WD1002-05). 

The HIL passes DATA and COMMANDS to the EDS 
and CP along with processed strobes derived from 
WE, RE, CS, and A2-A0 signals. HIL receives DATA 
and STATUS from the EDS and CP along with control 
information concerning DRQ and INTRQ generation. 



8-1 



HOST 
I/O BUS 



DAL7-DAL0 



-CONIROLS 



mwfy> 



DRQ, 
INTRQ (2) 



HOST 

INTERFACE; 
LOGIC 
(HIL) 



A 



CO 

ro 



i 



20 MHZ □ 



s 



iz 



RAM 
COUNTERS 



I 



(10) 



SECTOR 
BUFFER 
(SB) 

1KX8 



c 



c> 



iZ 







WD1015 
CONTROL 
PROCESSOR 
(CP) 




WD1014 
ERROR 
DETECTION/ 
SUPPORT LOGIC 
(EDS) 



I 



! 



^> 



WD1010 

WINCHESTER 

DRIVE 

CONTROLLER 

(WDC) 




DATA 

SEPARATOR/ 
WRITE 
PRECOMP, 



SDH LATCH, 
WINCHESTER 
DRIVE BUFFER 
INTERFACE 
(WDBI) 



-MFMRD 



A 



+ MFMRD 



-MFMWD 



+ MFMWD 



HD0-HD2 (3) 



DS1-DS3 (3) 



WG 



RWC 



STEP PULSE 



DIR IN 



WINCHESTER 
> DRIVE I/O 
' (MAX 3 
DRIVES) 



INDEX 



TR000 



SEEK COMP 



WRITE FLT 



Ready 



J 



^> 



%mfy 



L_- W 



WD2797 
FLOPPY DRIVE 
CONTROLLER 
(FDC) 



W^^^ 



CLOCK 
GENERATOR 



1 MHZ 



2 MHZ 



5 MHZ 



10 MHZ 




DATA BUS 
CONTROL BUS 



FLOPPY DISC 
DRIVE BUFFER 
INTERFACE 
(FDBI) 



READ DATA " ^ 



TK00 



INDEX 



WRITE PROTECT 



READY 



SIDE SELECT 



STEP 



. FLOPPY DISC I 
> DRIVE I/O 



DIRIN 



WD 



MOTOR ON 



WG 



DS0-DS3 (4) 



(MAX 4 
DRIVES) 



J 



'NOTONWD1002-HDO 



_J 



Figure 8-1. WD1002-05/WD1002-HDO Functional Block Diagram 



8.2.2 CONTROL PROCESSOR (CP) 

The main control center of the WD1002-05 is the CP 
(WD1015), used in conjunction with the EDS 
(WD1014) device, the clock generator, and the task 
files (TSF). The EDS device is the right hand of the CP 
and of sufficient complexity to be treated as a 
separate functional entity. 

The CP controls the transfer of information within the 
WD1 002-05 and maintains the necessary copies of 
the TSF found on both drives. Host access to the 
WD1 002-05 causes the CP to access task file infor- 
mation in the TSF after a command is issued. The 
TSF are physically located in the controller chips and 
on-board external logic is used to reflect any 
changes such as error and status information re- 
quired to integrate the floppy format to that of the 
Winchester controller. Depending upon the com- 
mand, the CP will make the buffer accessible to the 
host, the WD1010, or the WD2797 controllers. 

The CP also controls the operation of the Error Cor- 
recting iogic. During the transfer of data from the 
host to the WD1010, the EDS monitors the data bus, 
(if so enabled), to compute a 4-byte ECC which is ap- 
pended to the end of the data transferred to the 
WD1010 and recorded on the disc. During data trans- 
fers from the WD1010 to the host, the CP uses the 
ECC to validate the data. If the data is corrupted, the 
CP envokes recovery techniques such as retries and 
correction. A maximum of eight retries are attempted 
if two consecutive syndromes do not match. Correc- 
tion is attempted only if two consecutive syndromes 
match. If the error is uncorrectable, the operation is 
terminated. 

The CP is also used to handle data transfers to and 
from the SF for the floppy disc controller, which only 
uses CRC check byte for its data fields. 

During status reads by the host, the CP consolidates 
the normal completion status from the WD1010, the 
WD2797, and the current EDS status into a form con- 
sistant with established WD1010 error reporting for- 
mat. This consolidated status is then presented to 
the host. 

8.2.2.1 Clock Generator 

The 20 MHz oscillator drives the Clock Generator 
which provides all timing clocks for the WD1002-05. 

The crystal frequency divided by 2 is used as a refer- 
ence clock (2XDR) and then divided again by 2 for a 
1X clock (WCLK) which is used to clock the WD1010. 

The Floppy Disc Controller (WD2797) operates with a 
1 MHz clock for 5.25" drives. 2XDR divided by 10 is 
used to produce the required 1 MHz clock. 



The CP uses a 10 MHz clock (2XDR), giving an 
instruction cycle time of 1.5 ps. Most instructions 
execute in 3.0 jus, or two cycles. 

8.2.2.2 Task/Syndrome File (TSF) 

The TSF provides on-chip storage of the required 
task files for the WD1010/WD2797 controllers, and 
the 4 bytes of syndrome used for ECC. The check/ 
syndrome bytes are physically stored in the ECC gen- 
erator/checker. The WD1014 (EDS) maintains its own 
command register which serves also as an error reg- 
ister upon command completion. All other registers 
comprising the TSF are physically part of the 
WD1010 and WD2797 controllers. The CP controls all 
access to the TSF. Refer to separate sections on task 
files for their use. 

8.2.3 ERROR DETECTION AND SUPPORT 
LOGIC (EDS) 

The WD1014 EDS chip provides the WD1 002-05 with 
Error Correction Capabilities (ECC) and support 
logic. The EDS chip is a single chip device 
specifically designed to add ECC to the 5.25" 
Winchester disc drives. The EDS also contains three 
8-bit registers, three counters, and several latches 
that enhance the CP capabilities for control func- 
tions in a real time operation. This 40 pin chip 
replaces approximately 35 TTL packages consisting 
of shift registers, flip-flops, and combinatorial logic 
gates. 

8.2.3.1 Error Detection 

The EDS processes all data transfers in either direc- 
tion between the SB and the WD1010, if SDH bit 7 is 
set. This bit should only be set for hard disc opera- 
tion. The EDS generates the ECC/SYN DROME bytes 
by using a polynomial division process which can 
provide unique code words for long streams of data. 
The polynomial selected is a computer generated 
code optimized for sector sizes of 128, 256, 512, and 
1024 byte data fields. During Normal/Write operation, 
this division process produces a 32-bit remainder 
which is used as the four ECC bytes. In Normal/Read 
operation, the ECC bytes are recomputed and 
compared to the recorded ECC bytes to generate the 
Four SYNDROME bytes. If the syndrome is zero, 
there were no errors detected. Otherwise, the non- 
zero syndrome is used by the CP to compute the dis- 
placement of the error vector within the bad sector. 
This information is then used to correct the data if a 
single burst of no more than 5 bits in error occurred. 

During a WRITELONG operation, the EDS is inhibited 
from computing the 32 bit ECC word. The EDS then 
accepts a 32-bit appendage from the host and passes 



8-3 



it on, unaltered, to the WD1010 to be recorded on the 
disk. This permits the host to induce errors anywhere 
in the data stream so that the operation of the EDS 
can be validated during a subsequent READSHORT 
operation. 

During a READLONG operation, the EDS is inhibited 
from producing a syndrome. Instead, it copies the re- 
corded ECC check bits and passes them unaltered to 
the host, appended to the end of the sector data 
being read. As with WRITELONG, this command is 
useful when validating EDS performance. 

The EDS uses a 2-bit serial implementation of the 
generator polynomial during ECC generation and 
error detection. During correction operations, a serial 
reverse polynomial is used by the CP to compute the 
error vector and displacement. Correctable errors are 
corrected in the buffer without host intervention. Un- 
correctable errors are reported to the host and the un- 
corrected data is transferred to the host for further 
action. 

8.2.3.2 Support Logic 

The support logic consists of two 8-bit latches (com- 
mand/error register and SDH latch). Data requests, 
interrupts, BUSY, multiple mode, and read command 
information is also maintained and updated in the 
WD1014 to enhance the capability of the CP to 
handle control functions in real time. 

The EDS controls the buffer counter, incrementing 
and presetting due to commands from the host, and 
contains all the necessary logic to handle sector buf- 
fer overflow. Data, buffer addresses, and Drive/Head 
select control are handled by the same multiplexed 
8-bit address and data bus. 

8.2.4 SECTOR BUFFER (SB) 

The SB is used to buffer a sector of data being trans- 
ferred to or from the host. The sector size may be 
programmed for 128, 256, 512, or 1024 bytes. Thus, 
the minimum RAM size required is 1KX8. The ad- 
dress counters are controlled by the CP and EDS. All 
control signals for SB access are provided by the 
WD1010, or the CP when communicating with the 
floppy controller (WD2797). 

8.2.5 WINCHESTER DRIVE AND BUFFER 
INTERFACE (WDBI) 

The WDBI consists of the Winchester Disc Controller 
(WD1010), an 8-bit SDH latch, write precomp logic 
(WPC), data separator, and appropriate drivers and re- 
ceivers. The WD1010 is connected to the Winchester 
drives and the SB by means of 20 signal lines that 
form the WDBI. As previously mentioned, the 



WD1002-05 uses a multiplexed data/address bus to 
share SB access and control lines with the WD1010. 
Proper use of this interface results in having only a 
presettable counter to control the buffer and a 
latch/decoder to control up to three Winchester 
drives. The counter is preset using two separate 
strobes, one for each byte of the address, one 8-bii 
counter package provides addressing capability for a 
128 or 256 byte sector buffer size. By using more than 
one counter package, the WD1002-05 permits a multi- 
ple sector buffer size of 64K bytes. The SDH latch is 
used to provide drive selects 1-3 and head selects 0-7. 

8.2.5.1 Write Precompensation (WPC) 

The generation of Modified Frequency Modulation 
(MFM) write data takes place in the WD1010. This 
device accepts a byte of data and a WCLK to produce 
MFM data through internal circuitry which decides 
when and where to write clocks and data on the data 
stream under the MFM encoding rules. The MFM 
data stream is now totally compatible with the 
recording rules and may be sent to suitable line 
drivers for transmission to the drive except for one 
modification. Due to the decreasing radius on the 
physical surface of the disk, the inside tracks have 
less circumference and therefore exhibit a increase 
in recording flux density over the outside tracks. This 
increase in flux density aggravates a problem in 
magnetic recording known as 'dynamic bit shift.' 

Dynamic bit shift comes about as the result of one bit 
on the disk (a flux reversal) influencing an adjacent 
bit. The effect is to shift the leading edge of both bits 
closer together or further apart than recorded. The 
net result is that enough jitter is added to the data 
recorded on the inside tracks to make them harder to 
recover without error. 

Write precompensation is used to reduce the effect 
of dynamic bit shift. It is a way of predicting which 
direction a particular bit will be shifted and inten- 
tionally writing that bit out of position in the opposite 
direction to the expected shift. This is done by 
examining the next two data bits, the last and the 
present bits to be written and producing three sig- 
nals depending on what these bits are. The three 
signals are EARLY, LATE and NOMINAL. They are 
used in conjunction with a delay line to cause the 
leading edge of a data or clock bit to be written 
earlier, later, or on time. 

The processor can enable or disable the generation 
of these signals by controlling the Write Pre-Comp 
(WPC) line from the addressable latch. When WPC is 
high, precomp is in effect. When WPC is low, no 
precomp is generated and the nominal output of the 
device is held true. 



8-4 



8.2.5.2 Data Separator 

Data is recorded on Winchester discs using an MFM 
technique. This technique requires clock bits to be 
recorded only when two successive data bits are 
missing in the serial data stream. The fact that clock 
bits are not recorded with every data bit cell requires 
circuitry that can remain in sync with data during the 
absence of clock bits. Synchronous decoding of 
MFM data streams requires the decoder circuitry to 
synthesize clock bit timing when clock bits are miss- 
ing and synchronize to clock bits when they are pres- 
ent. This is accomplished by using a phase-locked 
oscillator employing an error amplifier and filter to 
sync onto and hold a specific phase relationship to 
the data and clock bits in the data stream. The phase- 
lock occurs at 2x average data rate frequency (f ), 
which in turn is used to synthesize a clock called 
RCLK with a frequency =1/2 fo. This synthesized 
clock can then be used to separate data bits from 
clock bits with external logic to shift the resultant 
serial data into registers for byte parallelization 
within the WD1010. 



8.2.6 FLOPPY DRIVE AND BUFFER 
INTERFACE (FDBI) 

The FDBI consists of a Floppy Disc Controller 
(WD2797), a drive select latch, head load, motor-on, 
buffer management logic, and appropriate drivers 
and receivers. The write precomp and data separator 
are internal to the WD2797. The WD1 002-05 can 
support up to four 5.25" floppy drives, double density 
and single or double sided (VVD1002-05 only). 



8-5 



SECTION 9 
MAINTENANCE 



9.1 GENERAL 

When the board is shipped from the factory, all ad- 
justments have been made using ST506 and SA450 
drives. The user need not make any adjustments if 
the drives supported are compatible with the fore- 
mentioned drives. 

There are four adjustments associated with the 
WD1 002-05 on-board data separation/write precomp 
circuitry and Vco tnat might have to be made if a 
drive with a different data rate is installed. On the 
WD2797, the write precompensation value is 
adjustable and the data separator might have to be 
adjusted for drives of different data rates. 

9.2 OSCILLATOR FREQUENCY 

Data separation circuitry on the WD1 002-05 uses a 
voltage-controlled oscillator (V c0 ) which phase-locks 
onto incoming data and provides a clock suitable for 
separating data and clock bits on an MFM-encoded 
data stream. The V co must be adjusted using the fol- 
lowing procedures: 

Connect a frequency counter to Test Connector 
U30-10(V co OUT). 

Connect a DVM to Test Connector U30-1 (V c i IN). 

Make all connections to the board, including the host 
and drive. Adjust the variable capacitor C19 until the 
frequency output locks onto the desired center fre- 
quency for the drive being used which is 10.000 MHz 
for ST506 or compatable drive. Once this "locked-on" 
frequency is achieved, continue the same adjust- 
ment for an input voltage of 2.5 ± 0.5 V. 

To complete the adjustment, monitor RCLK and 
RDATA inputs to the WD1010 (1119-39,37 respectively) 
and fine tune variable capacitor C19 until the rising 
edge of RDATA is exactly centered in either Half 
Phase or RCLK. 



■200 NSEC NOM- 



RCLK 



-*3- 



RDATA 



-Jf- 



i i 

h— ti »j« t 2 — ►[ 

u = t 2 
m + 1 2 = t 3 



-11- 



9.3 WD2797 ADJUSTMENT PROCEDURE 

WRITE PRECOMPENSATION 

Strobe MR (U15-19). 

Jumper across E3-E4. 

Observe pulse width on WD (U15-31). 

Adjust WPW (U15-33/R24) for desired pulse width 
(Precomp Nominal Value). 

DATA SEPARATOR 

Observe pulse width on TG43 (U15-29). 

Adjust RPW (U15-18/R25) for 1/8 of the read clock 
(500 ns for 5.25" DD). 

Observe frequency on DIRC (U15-16). 

Adjust variable capacitor (C7) on Vco P' n (U15-26) for 
Data Rate (250 KHz for 5.25" DD) 

Remove jumper between E3-E4. 

Note: To maintain interval Vco operation, insure that 
TEST = 1 whenever a Master Reset pulse (MR) is 
applied. 

9.4 TEST/OPERATION JUMPER VARIATIONS 



1. E1toE2 

2. E16toE15 

3. E4toE3 

4. E8/E10toE9 



N.A. 

N.A. 

Normally open. Ground for 
Floppy Write Precomp/Data 
Separator adj. only. 

GND (E8-E9) = No Write 

Precomp. 

Open = Write Precomp always. 

E10 to E9 = Write Precomp 

above TG43. 



5. 


E5/E7toE6 


E5 to E7 = Normal READ\ 

latch. 

E6 to E7 = If FRDY line avail 

able from Floppy drive. 


6. 


E11toE12 


GND = 40msec MOM delay. 
OPEN = 1 sec MOM delay. 


7. 


E13toE14 


N.A. 


8. 


E17/E19toE18 


E18toE19 = 10 MHz. 
E18toE17 = 20 MHz. 


9. 


E20toE21 


N.A. 


10. 


E22toE23 


N.A. 


11. 


E24toE25 


N.A. 



9-1 



APPENDIX A 
DISK DRIVER EXAMPLES 



A.1 INTRODUCTION 

The two sample disk drivers presented in this appendix are intended to serve as a catalyst to help the user set up 
his own first driver. Note that although the drivers shown are simplistic, they represent everything needed to 
satisfy WD1002-05 operating requirements. Retry software is not included in the examples because all 
necessary retries are performed by the WD1 002-05. 

The first example shown is a programmed I/O and polled status driver using the 8-bit Intel 8085 microprocessor. 
The second example is of a programmed I/O and interrupt driven driver and is written for the 16-bit Western 
Digital WD16 microprocessor. 

A.2 POLLED STATUS DRIVER 

• ••••••••••••••••••••••••••••■A-**********-******* 



WD1 002-05 Hard Disk Controller Driver 

Example for 8085 Microprocessor 
with programmed I/O and polled status 

• •••••••••••••••••••••••••••••••■A-************** 

;This driver is intended to demonstrate one simple approach to writing a 
;driver for the WD1002-05. It assumes that the WD1002-05 is interfaced using 
;programmed I/O without interrupts. 

;The specifications of the imaginary demonstration drive are: 

;Sector size: 256 bytes 

;Sectors per track: 33 

;Surfaces per drive: 4 (two platters) 

;Cylinders per drive: 512 

;Stepping rate: 2 milliseconds 

STRATE = 2 ;Define stepping rate for assembler 

As the WD1002 is being allowed to map around the bad blocks, one 
sector per track has to be sacrificed. This brings down the logical 
sector per track count to 32. 

Experienced systems programmers will note that the driver is not 

being made as flexible as it should be. As WD1002-05 compatible drives will 

be introduced in the future, and present manufacturers will be 

increasing the density of their current drives, the driver written 

should be built with sufficient equates and conditional 

assemblies. 

The imaginary operating system of this example can access up to 65536 
logical records of 256 bytes each. It has three types of calls: 
initialize, read, and write. Three numerical parameters are passed 
in the following registers: 

Drive number C 

Logical record number DE 

Transfer address H L 

Upon completion of all commands, the carry bit of the 8085 will be 
reset if the operation terminated properly and set if there was an 
error. If there was an error during read or write, the error-handling 
routine will decode it and print it out on the user console. 



A-1 



J************************5 




1 EQUATES ; 




^•••••••••••••••••••••••J 




; * * * Port Definition * * * 




BASADD = 


OC8 


;Base address of WD1 002-05 


DATA 


BASADD 


;Data register 


ERROR = 


BASADD + 1 


; Error Register 


WPC 


BASADD + 1 


;Write Precomp 


SECNT = 


BASADD + 2 


;Sector Count 


SECNO = 


BASADD + 3 


;Sector Number 


CYLLO = 


BASADD + 4 


;Cyiinder Number 


CYLHi 


BASADD + 5 


;CyiinderHigh 


SDH 


BASADD + 6 


;Size/Head/Drive 


STATUS = 


BASADD + 7 


;Status register 


COMND = 


BASADD + 7 


;Command register 


; * * * Command Definition * * * 




REST 


10 


; Restore command 


READ 


20 


;Read command (programmed I/O mode) 


WRITE 


30 


;Write command 



A.2.1 INITIALIZATION 



• •••••••••••••••••••a-** 



INITIALIZE 



*••*****•********•*•••• 



;This routine is called once whenever the system is powered up or reset. 
;lt sets the stepping rate and restores the head on the selected drive. 



RESTOR: 


CALL 


UPTASK 




MVI 


A,REST + <STRATE*2> 




OUT 


COMND 


RSWAIT: 


IN 


STATUS 




ANA 


A 




JM 


RSWAIT 




RAR 






RET 





;Select drive, don't care about record 
;Get stepping rate and restore 
;Output command to WD1 002-05 
;Wait 'till restore done 
;by updating sign flag in 8085 
;and wait 'till bit 7 (Busy) goes low 
;Put error bit in carry 
;Return to operating system 



A.2.2 READ SECTOR 



••***•**•*•*****•*****• 



READ 



*•**■*■***********•*■****■ 



;This is the read routine for the imaginary operating system. 



READIT: CALL UPTASK 

MVI A, READ 

OUT COMND 

;Wait for WD1 002-05 to read in a sector 

RWAIT: IN STATUS 

ANA A 

JM RWAIT 



;Update WD1002-05 task file 

;Get READ command 

;Output command to WD1 002-05 

;Check Busy bit 

;by updating sign flag in 8085 

;and wait 'ti!! bit 7 goes Sow 



A-2 



;Transfer sector from WD1 002-05 to system memory 
;(Transfer address in HL) 



MVI 


B,0 


READLP: IN 


DATA 


MOV 


M,A 


INX 


H 


DCR 


B 


JNZ 


READLP 


IN 


STATUS 


JMP 


DONE 



;lnit byte counter to 256 bytes 
;Get a byte of data from WD1 002-05 
;Move it to memory 
increment memory pointer 
;Decrement byte counter and continue 
;if we haven't transferred 256 yet 
; Re-read status for errors 
;Now check the completion status 



A.2.3 WRITE SECTOR 



,•••*••••*••••**•*•••*•*• 



WRITE 



,••••**•*•••*•••*•*•**••• 



;This is the write routine for the driver 



WRITIT: 



CALL 

MVI 

OUT 



UPTASK 
A,WRITE 
COMND 



;Update WD1002-05 task file 

;Get WRITE command 

;Output command to WD1 002-05 



;Transfer sector from system memory to WD1 002-05 
;(Transfer address in HL) 



WRITLP: 



MVI 

MOV 

OUT 

INX 

DCR 

JNZ 



B,0 

A,M 

DATA 

H 

B 

WRITLP 



;Wait for WD1 002-05 to write the sector 



WWAIT: 



IN 

ANA 

JM 



STATUS 

A 

WWAIT 



I nit byte counter to 256 bytes 
Get a byte of data from memory 
Move it to WD1 002-05 
Increment memory pointer 
Decrement byte counter and continue 
if we haven't transferred 256 yet 

;Check Busy bit 

;by updating sign flag in 8085 

;and wait 'till bit 7 goes low 



•**••*••*•***•***•*••• 



DONE 



,*•••**•**••*•••*•*•••*• 



;Both READ and WRITE commands finish here to check for errors 

DONE: RAR ; Rotate Error bit to carry 

RNC ;and return to OS if no error 

IN ERROR ;GetWD1002-05 error code 

;<«Place error reporting routine here>» 

STC ;Set carry to flag an error 

RET ;and return to OS with error 



A-3 



A.2.4 TASK FILE UPDATING 



•**•**•*•••**•••*•**•••••*•*•*•• 

UPTASK SUBROUTINE 

• •••••••••••••••••it************** 

;This subroutine sets up the task file registers 
;Sector number 



UPTASK: MOV 


A,E 


ANI 


31. 


OUT 


SECNO 


;Size/Drive/Head 




MOV 


A,E 


RLC 




RLC 




RLC 




ANI 


3. 


MOV 


B,A 


MOV 


A,C 


ADD 


A 


ADD 


A 


ADD 


A 


ORA 


B 


ORI 


80 


OUT 


SDH 


;Cylinderlow 




MOV 


A,E 


RAL 




MOV 


A,D 


RAL 




OUT 


CYLLO 


;Cylinderhigh 




MVI 


A,0 


RAL 




OUT 


CYLHI 


RET 




END 




A.3 INTERRUPT DRIVEN DRIVER 



;Get lower 8 bits of record number 
;Mask off lower 5 bits (bits 0-4) 
;and send to sector number register 



;Get lower 8 bits again 

; Rotate remaining 3 bits 

;to get an effective right shift of 5 

;Mask off next two bits (5-6) 

;to make head number 

;and store it away momentarily 

;Get drive number 

;and left shift it by 3 



OR in head number and 
OR in ECC flag and size field 
send it to Size/Drive/Head register 

;Get last bit of lower record number 
;and put it in carry 
;Get upper half of record number 
;Left shift it and merge in carry 
;Send it to lower cylinder register 

;Clear all bits except for the 
;the least significant and send 
;to the upper cylinder register 



**•*•••*•*••••*****•**************•*•*********** 

WD1 002-05 Hard Disk Controller Driver 

Example for the Western Digital 

WD16 Microprocessor 

using interrupts and programmed I/O 

• ••••••••••••••••••••••••••••it***************** 

;This example driver demonstrates the type of driver that would be 
;used in a multitasking environment. Like the 8085 driver, it uses pro- 



A-4 



;grammed I/O for data transfers. Unlike the last driver, this one 
;supports interrupts. 

;This new driver uses the same drive used in the 8085 example. 

;l_ike the last driver, this one can access up to 65536 logical records 
;of 256 bytes each. It still has three types of calls: initialize, read, 
;and write. Three numerical parameters are passed in the following 
; registers: 

; Drive number R1 

; Logical record number R2 

; Transfer address R3 

;Upon completion of all commands, the carry bit of the WD16 will be 
;reset if the operation terminated properly and set if there was an 
;error. If there was an error during read or write, the error-handling 
;routine will decode it and print it out on the user console. 



^•••••••••••••••••••••***5 






EQUATES ^ 




!***••*••*••**•***••*••*•; 




;*** Port Definition *** 




BASADD 


= 


OFFD8 


;Base address of WD1 002-05 


DATA 


= 


BASADD 


;Data register 


ERROR 


= 


BASADD + 1 


; Error Register 


WPC 


= 


BASADD + 1 


;Write Precomp 


SECNT 


= 


BASADD + 2 


;Sector Count 


SECNO 


= 


BASADD + 3 


;Sector Number 


CYLLO 


= 


BASADD + 4 


;Cylinder Number 


CYLHI 


= 


BASADD + 5 


;CylinderHigh 


SDH 


= 


BASADD + 6 


;Size/Head/Drive 


STATUS 


= 


BASADD + 7 


;Status register 


COMND 


= 


BASADD + 7 


;Command register 



; * * * Command Definition * • • 

REST = 10 

READ = 20 
WRITE = 30 

; * * * Drive stepping rate * * * 

STRATE = 2 

A.3.1 INITIALIZATION 

•*****••*****•••*••*+•• 

INITIALIZE 

•••**•*•***•**•******•• 



; Restore command 

;Read command (programmed I/O mode) 

;Write command 



;Drive stepping rate 



;This routine is called once whenever the system is powered up or reset. 
;lt sets the stepping rate and restores the head on the selected drive. 

RESTOR: CALL UPTASK ;Select drive, don't care about record 

;As a multitasking computer is being interfaced with, 

;the calling job should be put to sleep while the restore is being done. 

;The SLEEP instruction in this listing is actually a monitor call to 



A-5 



;the operating system which does the dirty work. Once the WD1002-05 has 
;completed the restore, it will interrupt the CPU and the interrupt 
jroutine will wake the job. Putting the job to sleep will allow other 
•taoj^e to mco tho CPU while the restore is in n ro n ress. 

LOCK 






SLEEP 
MOVB 
RORB 
RTN 

A.3.2 READ SECTOR 



IOWAIT 

@#STATUS,RO 

RO 



;Disable interrupts until sleep 

,vaci oicppn iy icuo at iu icoiuic 

;and output command to WD1 002-05 
;Put job in an I/O wait state 
;Get status register 
;Put error bit in carry 
;Return to operating system 



*•***•*•*•*****•**•**•• 

READ 

••••*•••*••**•**••****• 



;This is the read routine for the imaginary operating system. 



READIT: 



CALL 
LOCK 
MOVB 



UPTASK 



;Update WD1002-05 task file 
;Disable interrupts 'til we go to sleep 
;lssue READ command to WD1 002-05 



;While waiting, go into I/O wait state 



#READ,@#COMND 

;Wait for WD1002-05 to read in a sector 

SLEEP IOWAIT 

;After wakeup, transfer sector from WD1 002-05 to system memory 
;(Transfer address in R3, WD1002-05 data register address in R4) 

MOV #256.,RO ;lnit byte counter to 256 bytes 

;The following instruction, MABB (Move Address to Block of Bytes), does 
;a block move by reading the data pointed to by R4 (WD1 002-05 data 
;register) and puts them in a block of memory pointed to by R3. R0 bytes 
;are moved. 

MABB R4,R3 ;Move data from WD1 002-05 to memory 

BR DONE ;Now check the completion status 

A.3.3 WRITE SECTOR 

*•*•*********•*••***•••*! 

WRITE | 

••••••••••••••••••••••••I 

;This is the write routine for the imaginary driver 

WRITIT: CALL UPTASK ;Update WD1002-05 task file 

MOVB #WRITE,@#COMND ;lssue WRITE command to WD1002-05 

;Transfer sector from system memory to WD1 002-05 
;(Transfer address in R3, WD1002-05 data register address in R4) 

MOV #256.-1 .,RO ;lnit byte counter to 256-1 bytes 

;The following instruction, MBBA (Move Block of Bytes to Address) is the 
jconverse of the MABB instruction, above. This time the block of memory 
jpointed to by R3 will be moved to the WD1 002-05 data register (pointed to 
;by R4). R0 bytes will be moved. 



A-6 



MBBA R3,R4 

LOCK 

MOVB @R3,@R4 

;Wait for WD1 002-05 to write the sector 

SLEEP IOWAIT 



Move most of the data 

Disable ints. 'till last byte xferred 

Write last byte of data to WD1 002-05 

;Wait in I/O wait state 



i*********************** 



DONE 



i*********************** 



;Both READ and WRITE commands finish here to check for errors 



DONE: MOVB @#STATUS,R0 

RORB R0 

BCC DONEOK 

MOVB @#ERROR,R0 

;<«Place error reporting routine here>» 

LCC CARRY 

DONEOK: RTN 

A.3.4 TASK FILE UPDATING 



;Get status byte from WD1 002-05 
; Rotate Error bit to carry 
;and return to OS if no error 
;Get WD1 002-05 error code 



;Set carry to flag an error 
;and return to OS with error 



UPTASK SUBROUTINE 

I******************************** 



;This subroutine sets up the task file registers 



;Sector number 



UPTASK: 



MOV 
AND 
MOV 
MOVB 



R2.R0 
#31.,R0 
#SECNO,R4 
R0,(R4) + 



;Get record number 

;Mask off lower 5 bits (bits 0-4) 

;lndex WD1002-05 sector number register 

;and send to sector number register 

;and increment R4 to point to WD1 002-05 

;Cylinder Low register 



;Size/Drive/Head 

;(The following instruction does a right arithmetic shift 5 times) 



Discard SECNO bits from record number 
Get remaining record number bits 
Mask off bits 5-6 to make head number 



SSRA R2,5 

MOV R2,R0 

AND #3.,R0 
;(The following instruction does a left arithmetic shift 3 times) 

SSLA R1 ,3 ;Shift drive number into position 

OR R1 ,R0 ;OR drive number and head together 

OR #80,R0 ;OR ECC flag and sector size field 

MOVB R0,@#SDH ;send it to Size/Drive/Head register 



;Discard HEAD bits from record number 
;Send Cylinder Low to WD1 002-05 and 
;increment R4 to point to Cylinder High 



Cylinder Low 




SSRA 


R2,2 


MOVB 


R2,(R4) + 



A-7 



;Cylinder High 

;(The following instruction SWAps the upper and lower Byte of a word) 



SWAB R2 

AND #1,R2 

MOVB R2,(R4) 

MOV #DAiA,m4 
RTN 



Get upper byte of cylinder 

Mask to least significant bit 

and send it to WD1 002-05 

index VVDi 002-05 Data Reg for R/VV ops 



A.3.5 INTERRUPT SERVICE ROUTINE 



• •***••• + ***••***•*••**••*••••■*-*•••*•**, 

INTERRUPT SERVICE ROUTINE 

••••••••••••••••••••••••••••••••••••••*5 



;This routine gets called whenever the WD1 002-05 interrupts. All it does is 
;read the status register of the WD1002-05 to clear INTRQ and revives the 
joriginal calling job. 



INTSER: PUSH R0 

MOVB @#STATUS,R0 

WAKEUP IOWAIT 

POP R0 

RTT 

END 



;Save this register 

;Acknowledge the interrupt to WD1002-05 

;Wake up job (from I/O wait state) 

; Return from trap 



A-8 



APPENDIX B 
INTERLEAVE CALCULATING 



This BASIC program simplifies the process of generating interleave tables. It is written in a fairly standard 
subset of the BASIC language and should run on many BASIC interpreters and compilers. Some implementa- 
tions of BASIC may require the variable names to be converted to single letter names and the IF THEN ELSE 
constructs may have to be rewritten. 

The two questions at the beginning of the program should be answered in decimal. The interleave table is 
printed in hexadecimal. 

BASIC INTERLEAVE CALCULATING PROGRAM 

10 PRINT "WD1002-05 Interleave calculating program" 

20 PRINT 

30 INPUT "Number of sectors? ";COUNT 

40 INPUT "Interleave Factor? ";INTER 

50 DIM HEX$(16),SECTOR(COUNT) 

60 FORINDEX=1T016 

70 READ HEX$(INDEX) 

80 NEXT 

90 FOR INDEX = 1 TO COUNT 

100 SECTOR(INDEX)=-1 

110 NEXT 

115 RES = 

120 FOR INDEX = 0TO COUNT- 1 

130 IF RES>=COUNTTHENRES= RES-COUNT 

140 IF SECTOR(RES + 1) = - 1 THEN SECTOR(RES + 1) = INDEX ELSE RES = RES + 1 :G 

150 RES = INTER+RES 

160 NEXT 

170 PRINT 

180 PRINT "Interleave table with";COUNT;"sectors and";INTER;": 1 interleave" 

190 FOR INDEX = 1 TO COUNT 

200 X = INT(SECTOR(INDEX)/16) 

210 PRINT HEX$(X + 1);HEX$(SECTOR(INDEX)-X*16 + 1), 

220 NEXT 

230 PRINT 

240 DATA 0,1,2,3A5,6,7,8,9AB,C > D,E > F 

250 END 



B-1 



APPENDIX C 
CALCULATING SECTORS PER TRACK 



Changes in WD1 002-05 compatible disk drives consisting of higher bit-packing densities and higher accuracy 
spindle motors will increase the amount of data that can be put on a track. This appendix will help users 
determine the maximum number of sectors that can be recorded on their disk drive. 

The unformatted byte capacity can be figured from this formula: 

Capacity = Bits per second / Revolutions per second x (1-Error) / 8 

Assuming a hypothetical drive (the same one as in the disk driver examples) with a data rate of 5M bits per 
second, a revolution rate of 3600 RPM, and a spindle speed accuracy of 3%, these values applied to the 
foregoing formula yield: 

10,104 = 5 s 000,000/60x(1 - 0.03)/8 

To be on the safe side, a fractional value will always be rounded down. The unformatted capacity of this drive is 
10,104 bytes. To figure the number of sectors per some number of bytes apply this formula: 

Sectors = Capacity / (Data field size + Gap3 + Check bytes + Other overhead) 

Using 512 byte sectors with a Gap3 size of 30 bytes, running ECC results in: 

17=10,104/(512 + 30 + 4 + 41) 

The BASIC program on the next page can be used to automate the sector-per-track calculations presented here. 

BASIC SECTORS PER TRACK UTILITY 

10 PRI NT "WD100X Sectors per Track Calculating Utility" 

20 PRINT 

30 INPUT "Data rate of drive in bits per second: "; DATARATE 

40 INPUT "Revolutions per minute: ";RPM 

50 INPUT "Rotational speed error in percent: ";RERROR 

60 CAPACITY = INT(DATARATE/RPM*60*(1 - RERROR/100)/8) 

70 PRINT "Unformatted capacity is"CAPACITY"bytes." 

80 PRINT 

90 INPUT "Data field size in bytes (128, 256, etc.): ";SIZE 

100 INPUT "Formatted with CRC or ECC: ";ECCMODE$ 

110 ECCMODE$= LEFT$(UCS(ECCMODE$),1) 

120 IF ECCM0DE$O"E" AND ECCM0DE$O"C" THEN 100 

130 IFECCMODE$ = "E"THENCHECKBYTES = 4ELSECHECKBYTES = 2 

140 IF SIZE>256 THEN GAP3 = 30 ELSE GAP3 = 15 

150 SECTORS = INT(CAPACITY/(SIZE + GAP3 + CHECKBYTES + 41)) 

160 PRINT "Formatted capacity is"; SECTORS*SIZE;"bytes per track using"; 

170 PRINT SECTORS;"sectors per track." 

180 END 



C-1 



APPENDIX D 
PROGRAMMER'S QUICK REFERENCE 



D.1 TASK FILE 



BSY 


cso 


A2 


A1 


AO 


RE 


WE 


1 


X 


X 


X 


X 


Deselected 


Deselected 




















1 




1 




Data Register 
Error Register 
Sector Count 


Data Register 
Write Precomp* 
Sector Count 











1 


1 


Sector Number 


Sector Number 












1 
1 
1 





1 




1 




Cylinder Low 
Cylinder High** 
Size/Drive/Head 


Cylinder Low 
Cylinder High** 
Size/Drive/Head 








1 


1 


1 


Status Register 


Command Register 



* Not used on floppies 
** LSB of cylinder high, if set to 1, permits a 48 t.p.i. floppy disk to be read on a 96 t.p.i. floppy disk system. 

D.2 VALID COMMANDS 



TYPE 


COMMAND 


BITS 
7 6 5 4 3 2 10 




Test 


10 10 




Restore 


1 r3 r2 n ro 




Seek 


1 1 1 r3 r2 n ro 


II 


Read Sector 


1 D M L 


III 


Write Sector 


1 1 M L 


III 


Format Track 


10 10 



D.3 SDH REGISTER FORMAT 



Bit 
Function 



7 


6 5 


4 3 


2 1 


CRC/ 
ECC 


Sec 
Size 


Drive 
Select 


Head/Drive 
Select 



Bit 
6 


Bit 
5 


Sector Size 




1 
1 



1 

1 


256 Bytes 

512 Bytes 

1024 Bytes 

128 Bytes 



Bit 
4 


Bit 
3 


Drive Selected 
(decoded & latched) 




1 
1 



1 

1 


Drive Sel 1 
Drive Sel 2 
Drive Sel 3 
Floppy Dr Sel 



D-1 



Bit 


Bit 


Bit 


Head Selected 


2 


1 





Hard Disk 











HeadO 








1 


Head 1 





1 





Head 2 





1 


1 


Head 3 


1 








Head 4 


1 





1 


Head 5 


1 


1 





Head 6 


1 


1 


1 


Head 7 



Bit 


Bit 


Bit 


Floppy Drive & 


2 


1 





Head Select 











FD1 — HSO 








1 


FD1 — HS1 





1 





FD2 — HSO 





1 


1 


FD2 — HS1 


1 








FD3 — HSO 


1 





1 


FD3 — HS1 


1 


1 





FD4 — HSO 


1 


1 


1 


FD4 — HS1 



D.4 STATUS AND ERROR REGISTER BITS 



Bit 


Status Register 


Error Register 


7 


Busy 


Bad Block Detect 


6 


Drive Ready 


Uncorrectable Error 


5 


Write Fault 


— 


4 


Seek Complete 


ID Not Found 


3 


Data Request 


— 


2 


Corrected 


Aborted Command 


1 


Not used 


TR000 Error 





Error 


DAM not found 



D-2 



APPENDIX E 
LSI DATA SHEETS 



(to be supplied) 



E-1 



APPENDIX F 
SCHEMATICS AND ASSEMBLY DIAGRAMS 



F-1 



01 




t_ 

r 



+ SV (COMPONENT SIDE.) 
GND (SOLDER SIDE) 



CS-Cd.) Vto OUT 

(i- DB) Vco IN 

(4-C3) DRUN- 

(J-C2 WPCD- 

(5-B5) RD*T* 

(5D5) RC- 

(I-&S) T&41 

(I-B5) TEST- 



(l-Cl) 
U-B3) 



DIRF 
WOF 





1 

£ 

7 
9 

II 
15 



- MFMWD 
* MFMWD 



TOLERANCES 



WESTERN DIGITAL 



oi loaioso 

SCALE N/A 






a> 



R49, S.3K 
C2B, ISOf'f 




notes: Ai8 t:n gnd pins: i,a;i,9,ii,is,i5Ai9,2i,2?,"i 

27,29,51,53, 
/^\J5 GND PINS'. a-ABCEVEN PIN ONLY) 
3. Jl J2 Ji G>ND PINS: 2,4, (.,8, II, 12,15, iu, is, za. 
■4. ALL RESISTER VALUES. HR£ IN OHMS 

UNLESS OTHERWISE SPECIFIED. 
S. ADD .luf CAP FROM ALL It Vet TO GND. 
4:3 6nd PINS'. a,IO, | Z, | i/ l4 , ,5 < l <''• 
A CAP 3/E> PHYSICALLY CLOSE TO CHIP. 



DRUN- (J-A4-1 



fZ-Bil WG 



Ci-O.) V«.o OUT 



PUP22 

PUPA-7 

PUP5B 



!>R50 i R47 >R22 



ci-c(.,ca 
en. cmaz.at 
czy,ch\-u\a 



^,-L.Uf cis + i 



l 



CIS 
22 »f 



I-C 



GND 
GND 



ECO DESCRIf 



■4.YRIHRTE *-va 



WESTERN DIGITAL 



""■■SV4 WINCHESTER/ 5/* FLOPPY 
CONTROLLER SO. (WDIQ02-OS1 



loaioso loonl 



1^ 



k7_Uo 



.PC I...O.II1 «H«l„l ..i 



APPENDIX G 
BILL OF MATERIALS 



(to be supplied) 



G-1